公开(公告)号：US11763883B2

公开(公告)日：2023-09-19

申请号：US17568229

申请日：2022-01-04

Applicant: Kioxia Corporation

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/56 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

公开(公告)号：US12293787B2

公开(公告)日：2025-05-06

申请号：US18364524

申请日：2023-08-03

Applicant: KIOXIA CORPORATION

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/00 ,  G06F3/06 ,  G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H10B69/00

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

公开(公告)号：US11740794B2

公开(公告)日：2023-08-29

申请号：US17527851

申请日：2021-11-16

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Tokumasa Hara

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/0875 ,  G06F13/16 ,  G11C16/10 ,  G11C16/26 ,  G11C7/24

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0875 ,  G06F13/16 ,  G11C7/1063 ,  G11C16/10 ,  G11C16/26 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/452 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C7/24

Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.

公开(公告)号：US11551774B2

公开(公告)日：2023-01-10

申请号：US17178554

申请日：2021-02-18

Applicant: Kioxia Corporation

Inventor： Itaru Hida ,  Tokumasa Hara

IPC: G11C29/42 ,  G11C29/50 ,  G11C29/44

Abstract: According to one embodiment, a memory system includes a non-volatile memory provided with a plurality of memory cells, and a memory controller. The memory controller reads data subjected to error-mitigation encoding from the non-volatile memory, the data including determination information indicating whether or not a value is changed by the error-mitigation encoding, executes error-mitigation decoding on the read data, re-executes the error-mitigation encoding on a decoding result obtained by the error-mitigation decoding, and compares the determination information included in the read data with determination information included in data obtained by re-executing the error-mitigation encoding and outputs a comparison result.

公开(公告)号：US11264090B2

公开(公告)日：2022-03-01

申请号：US17014293

申请日：2020-09-08

Applicant: Kioxia Corporation

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06F3/06 ,  H01L27/115 ,  G11C16/04

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

公开(公告)号：US11238924B2

公开(公告)日：2022-02-01

申请号：US17016765

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: H03M13/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G06F11/10 ,  G11C16/10

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

公开(公告)号：US11226742B2

公开(公告)日：2022-01-18

申请号：US16883560

申请日：2020-05-26

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Tokumasa Hara

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/0875 ,  G06F13/16 ,  G11C16/10 ,  G11C16/26 ,  G11C7/24

Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.