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公开(公告)号：US12073885B2
公开(公告)日：2024-08-27
申请号：US18121344
申请日：2023-03-14
Applicant: Kioxia Corporation
Inventor： Hiroshi Sukegawa , Ikuo Magaki , Tokumasa Hara , Shirou Fujita
CPC classification number: G11C16/10 , G06F3/0604 , G06F3/064 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C16/3418 , H10B43/27
Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
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公开(公告)号：US11756611B2
公开(公告)日：2023-09-12
申请号：US17582330
申请日：2022-01-24
Applicant: Kioxia Corporation
Inventor： Tokumasa Hara , Noboru Shibata
CPC classification number: G11C11/56 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/0483 , H10B69/00
Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
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公开(公告)号：US11631463B2
公开(公告)日：2023-04-18
申请号：US17381248
申请日：2021-07-21
Applicant: Kioxia Corporation
Inventor： Hiroshi Sukegawa , Ikuo Magaki , Tokumasa Hara , Shirou Fujita
Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
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公开(公告)号：US11289167B2
公开(公告)日：2022-03-29
申请号：US17104564
申请日：2020-11-25
Applicant: KIOXIA CORPORATION
Inventor： Takayuki Akamine , Masanobu Shirakawa , Tokumasa Hara
Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
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公开(公告)号：US12176027B2
公开(公告)日：2024-12-24
申请号：US18467271
申请日：2023-09-14
Applicant: Kioxia Corporation
Inventor： Tokumasa Hara , Noboru Shibata
Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
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Patent Agency Ranking
公开(公告)号：US11688458B2
公开(公告)日：2023-06-27
申请号：US17561545
申请日：2021-12-23
Applicant: Kioxia Corporation
Inventor： Noboru Shibata , Tokumasa Hara
CPC classification number: G11C11/5628 , G06F13/16 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C2211/5648
Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
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公开(公告)号：US11646076B2
公开(公告)日：2023-05-09
申请号：US17545470
申请日：2021-12-08
Applicant: Kioxia Corporation
Inventor： Tokumasa Hara , Noboru Shibata
CPC classification number: G11C11/5628 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G11C16/0483 , G11C16/10 , G11C16/14
Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.
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公开(公告)号：US11372719B1
公开(公告)日：2022-06-28
申请号：US17367189
申请日：2021-07-02
Applicant: Kioxia Corporation
Inventor： Yasuyuki Imaizumi , Tokumasa Hara , Toshiyuki Yamagishi
Abstract: A memory system includes a non-volatile memory including at least one memory cell, a buffer, and a memory controller. The memory controller acquires first data from the buffer. The first data includes a plurality of bits of data. The memory controller generates second data by performing a randomization process on the first data, generates a flag that is information used to identify an error suppression encoding process, based on the second data, and stores the flag in the buffer. The memory controller acquires third data and the flag from the buffer. The third data is 1-bit data of the first data. The memory controller generates storage data by performing the error suppression encoding process based on the acquired flag and the randomization process on the third data, and writes the storage data into the memory cell.
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9.发明授权公开(公告)号：US12164772B2
公开(公告)日：2024-12-10
申请号：US18348061
申请日：2023-07-06
Applicant: Kioxia Corporation
Inventor： Masanobu Shirakawa , Tokumasa Hara
Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
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公开(公告)号：US11967368B2
公开(公告)日：2024-04-23
申请号：US18295504
申请日：2023-04-04
Applicant: KIOXIA CORPORATION
Inventor： Tokumasa Hara , Noboru Shibata
CPC classification number: G11C11/5628 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G11C16/0483 , G11C16/10 , G11C16/14
Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.
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