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公开(公告)号：US08673738B2
公开(公告)日：2014-03-18
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/76
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
摘要翻译： 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。
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公开(公告)号：US08673708B2
公开(公告)日：2014-03-18
申请号：US13611044
申请日：2012-09-12
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/66795
摘要： A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.
摘要翻译： 一种方法包括提供绝缘体上硅晶片（例如，ETSOI晶片）; 形成覆盖牺牲绝缘体层的牺牲栅极结构; 形成与牺牲栅极结构相邻的凸起的源极/漏极; 沉积覆盖升高的源极/漏极并围绕牺牲栅极结构的层; 以及去除牺牲栅极结构，留下延伸到牺牲绝缘体层的开口。 该方法还包括加宽开口以暴露一些升高的源极/漏极，去除牺牲绝缘体层并在开口的侧壁上形成间隔层，间隔层仅覆盖暴露的升高的源极/漏极的上部 ，并且在开口内沉积一层栅介质材料。 栅极导体沉积在开口内。
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公开(公告)号：US20130249002A1
公开(公告)日：2013-09-26
申请号：US13424447
申请日：2012-03-20
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/84 , H01L29/66545
摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.
摘要翻译： 改进ETSOI MOSFET器件的结构和方法。 提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。
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公开(公告)号：US20130082308A1
公开(公告)日：2013-04-04
申请号：US13251757
申请日：2011-10-03
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.
摘要翻译： 公开了晶体管器件及其制造方法。 在一种方法中，在基板上形成虚拟栅极结构。 虚拟门结构的底部是底切的。 此外，在基板上形成阶梯状，凸起的源极和漏极区域，以及由底切形成的至少一个底切部。 去除虚拟栅极结构并在衬底上形成替换栅极。
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公开(公告)号：US20130034938A1
公开(公告)日：2013-02-07
申请号：US13611044
申请日：2012-09-12
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/66795
摘要： A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.
摘要翻译： 一种方法包括提供绝缘体上硅晶片（例如，ETSOI晶片）; 形成覆盖牺牲绝缘体层的牺牲栅极结构; 形成与牺牲栅极结构相邻的凸起的源极/漏极; 沉积覆盖升高的源极/漏极并围绕牺牲栅极结构的层; 以及去除牺牲栅极结构，留下延伸到牺牲绝缘体层的开口。 该方法还包括加宽开口以暴露一些升高的源极/漏极，去除牺牲绝缘体层并在开口的侧壁上形成间隔层，间隔层仅覆盖暴露的升高的源极/漏极的上部 ，并且在开口内沉积一层栅介质材料。 栅极导体沉积在开口内。
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公开(公告)号：US20130015525A1
公开(公告)日：2013-01-17
申请号：US13179990
申请日：2011-07-11
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02529 , H01L21/02532 , H01L21/0257 , H01L21/02592 , H01L21/0332 , H01L21/283 , H01L21/30604 , H01L21/31111 , H01L21/32053 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L29/0653 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/167 , H01L29/41783 , H01L29/45 , H01L29/665 , H01L29/6656
摘要： An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
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17.发明申请公开(公告)号：US20120040522A1
公开(公告)日：2012-02-16
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译： 公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。 该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。 因此，本公开的方法避免了短信道惩罚。 此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。
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公开(公告)号：US09087741B2
公开(公告)日：2015-07-21
申请号：US13179990
申请日：2011-07-11
IPC分类号： H01L27/12 , H01L21/84 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02529 , H01L21/02532 , H01L21/0257 , H01L21/02592 , H01L21/0332 , H01L21/283 , H01L21/30604 , H01L21/31111 , H01L21/32053 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L29/0653 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/167 , H01L29/41783 , H01L29/45 , H01L29/665 , H01L29/6656
摘要： An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
摘要翻译： 一种用于产生具有用于NMOS和PMOS的双凸起源极和漏极的CMOS的装置和方法。 两个堆叠门上的间隔物的厚度相同。 在该方法中，在表面上形成第一绝缘层。 然后第一区域被掩蔽，而另一区域具有蚀刻掉的第一层，并且在该区域上生长外延源和漏极。 第二层形成于所有暴露的表面。 然后在第一区域被蚀刻掉的同时掩蔽第二区域。 外延源极和漏极形成在第一区域上。 第二区域也可以通过加入一薄层未掺杂的硅然后氧化来掩蔽。 掩盖第二个区域的另一种方法是使用硬面罩。 形成第二源和漏极的另一种方法是使用无定形材料。
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公开(公告)号：US09059243B2
公开(公告)日：2015-06-16
申请号：US13531654
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/70 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
摘要翻译： 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。
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公开(公告)号：US08664050B2
公开(公告)日：2014-03-04
申请号：US13424447
申请日：2012-03-20
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/84 , H01L29/66545
摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.
摘要翻译： 改进ETSOI MOSFET器件的结构和方法。 提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 在第一半导体层上形成栅极结构，并且在涉及的湿清洗期间，STI纹路侵蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。
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