公开(公告)号：US06737683B2

公开(公告)日：2004-05-18

申请号：US10372079

申请日：2003-02-25

申请人： Kaoru Inoue ,  Yoshito Ikeda ,  Yutaka Hirose ,  Katsunori Nishii

发明人： Kaoru Inoue ,  Yoshito Ikeda ,  Yutaka Hirose ,  Katsunori Nishii

IPC分类号： H01L310328

CPC分类号： H01L29/66878 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/8126

摘要： A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.

摘要翻译： 半导体器件具有由III-V族氮化物半导体和欧姆电极构成的有源区域和分别形成在有源区域上的栅电极。 有源区域的整个表面暴露于等离子体，使得其中的电子的表面电位低于整个表面不暴露于等离子体的情况。

公开(公告)号：US07105907B2

公开(公告)日：2006-09-12

申请号：US10453045

申请日：2003-06-03

申请人： Yoshito Ikeda ,  Kaoru Inoue ,  Yutaka Hirose ,  Katsunori Nishii

发明人： Yoshito Ikeda ,  Kaoru Inoue ,  Yutaka Hirose ,  Katsunori Nishii

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/0328 ,  H01L29/80

CPC分类号： H01L29/66871 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/812

摘要： A buffer layer, an undoped gallium nitride layer, and an n-type gallium nitride active layer are formed on a sapphire substrate. Ohmic contacts and a Schottky contact are then formed on the n-type gallium nitride active layer as a source contact, a drain contact and a gate contact, respectively. The Schottky contact is a copper alloy, such as palladium copper, in which the content by weight of copper is 5%.

摘要翻译： 在蓝宝石衬底上形成缓冲层，未掺杂的氮化镓层和n型氮化镓活性层。 然后分别在作为源极接触，漏极接触和栅极接触的n型氮化镓有源层上形成欧姆接触和肖特基接触。 肖特基接触是铜合金，例如钯铜，其中铜的重量含量为5％。

公开(公告)号：US5872393A

公开(公告)日：1999-02-16

申请号：US738744

申请日：1996-10-28

申请人： Hiroyuki Sakai ,  Takayuki Yoshida ,  Yorito Ohta ,  Kaoru Inoue ,  Katsunori Nishii ,  Yoshito Ikeda

发明人： Hiroyuki Sakai ,  Takayuki Yoshida ,  Yorito Ohta ,  Kaoru Inoue ,  Katsunori Nishii ,  Yoshito Ikeda

IPC分类号： H01L23/498 ,  H01L23/66 ,  H05K1/00 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05599 ,  H01L2224/10135 ,  H01L2224/13011 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48463 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81007 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L24/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4676

摘要： In fabricating an MFIC by mounting a semiconductor chip on a substrate having a microstrip line by MBB bonding, a benzocyclobutene (BCB) film is used as a dielectric film of the microstrip line. By providing a means for preventing the deformation, peeling, and cracking of the BCB film during the fabrication process, the thickness of the dielectric film is held substantially equal even after flip-chip mounting, which reduces impedance fluctuations.

摘要翻译： 在通过MBB接合将半导体芯片安装在具有微带线的基板上制造MFIC时，使用苯并环丁烯（BCB）膜作为微带线的电介质膜。 通过提供在制造过程中防止BCB膜的变形，剥离和破裂的装置，即使在倒装芯片安装之后，电介质膜的厚度也保持基本相等，这降低了阻抗波动。

公开(公告)号：US07449399B2

公开(公告)日：2008-11-11

申请号：US11527695

申请日：2006-09-27

申请人： Kaoru Inoue ,  Yoshito Ikeda ,  Yutaka Hirose ,  Katsunori Nishii

发明人： Kaoru Inoue ,  Yoshito Ikeda ,  Yutaka Hirose ,  Katsunori Nishii

IPC分类号： H01L21/26

CPC分类号： H01L29/66878 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/8126

摘要： A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.

摘要翻译： 半导体器件具有由III-V族氮化物半导体和欧姆电极构成的有源区域和分别形成在有源区域上的栅电极。 有源区域的整个表面暴露于等离子体，使得其中的电子的表面电位低于整个表面不暴露于等离子体的情况。

公开(公告)号：US20070020896A1

公开(公告)日：2007-01-25

申请号：US11527695

申请日：2006-09-27

申请人： Kaoru Inoue ,  Yoshito Ikeda ,  Yutaka Hirose ,  Katsunori Nishii

发明人： Kaoru Inoue ,  Yoshito Ikeda ,  Yutaka Hirose ,  Katsunori Nishii

IPC分类号： H01L21/26 ,  H01L21/28

CPC分类号： H01L29/66878 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/8126

摘要： A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.

摘要翻译： 半导体器件具有由III-V族氮化物半导体和欧姆电极构成的有源区域和分别形成在有源区域上的栅电极。 有源区域的整个表面暴露于等离子体，使得其中的电子的表面电位低于整个表面不暴露于等离子体的情况。

公开(公告)号：US06933181B2

公开(公告)日：2005-08-23

申请号：US10620430

申请日：2003-07-17

申请人： Kaoru Inoue ,  Yoshito Ikeda ,  Katsunori Nishii ,  Yutaka Hirose

发明人： Kaoru Inoue ,  Yoshito Ikeda ,  Katsunori Nishii ,  Yutaka Hirose

IPC分类号： H01L21/316 ,  H01L21/335 ,  H01L29/20 ,  H01L29/778 ,  H01L21/00

CPC分类号： H01L29/66462 ,  H01L21/02178 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/31666 ,  H01L29/2003 ,  H01L29/7787 ,  Y10S148/113

摘要： In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950° C. or more and 1050° C. or less.

摘要翻译： 在制造半导体器件的方法中，首先在衬底上形成氮化镓铝的第一半导体层，然后在第一半导体层上形成包含硅的保护膜，使得器件隔离区域不被覆盖 。 此后，该方法还包括在温度调节在950℃以上且1050℃以下的氧化气氛中对第一半导体层进行热处理的工序。

公开(公告)号：US06531718B2

公开(公告)日：2003-03-11

申请号：US09759401

申请日：2001-01-12

申请人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

发明人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

IPC分类号： H01L2906

CPC分类号： H01L29/205 ,  H01L29/2003 ,  H01L29/7783

摘要： A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein surfaces of the buffer layer are c facets of Ga atoms; a separating layer including (InXAl1-X)YGa1-YN (where 0≦X≦1, 0≦Y≦1) formed on the buffer layer, wherein surfaces of the separating layer are c facets of In, Al, or Ga atoms; a channel layer including GaN, InGaN, or a combination of GaN and InGaN formed on the separating layer, wherein surfaces of the channel layer are c facets of Ga or In atoms; and an electron supply layer including AlGaN formed on the channel layer, wherein surfaces of the electron supply layer are c facets of Al or Ga atoms, wherein the AlN composition ratio in the separating layer is smaller than the AlN composition ratio in the electron supply layer.

摘要翻译： 半导体器件包括：衬底; 包括在衬底上形成的GaN的缓冲层，其中缓冲层的表面是Ga原子的c个面; 形成在缓冲层上的（InXAl1-X）YGa1-YN（其中0 <= X <= 1,0 <= Y <= 1）的分离层，其中分离层的表面是In，Al， 或Ga原子; 包含GaN，InGaN或在分离层上形成的GaN和InGaN的组合的沟道层，其中沟道层的表面是Ga或In原子的c个面; 以及形成在沟道层上的包含AlGaN的电子供给层，其中电子供给层的表面是Al或Ga原子的c个面，其中分离层中的AlN组成比小于电子供给层中的AlN组成比 。

公开(公告)号：US06812505B2

公开(公告)日：2004-11-02

申请号：US10605019

申请日：2003-09-02

申请人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

发明人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

IPC分类号： H01L29737

CPC分类号： H01L29/7783 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/42316

摘要： A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.

摘要翻译： 半导体器件包括：衬底; 包括形成在衬底上的GaN的缓冲层，其中：缓冲层的表面是Ga原子的c个面; 在缓冲层上形成包括GaN或InGaN的沟道层，其中：沟道层的表面是Ga或In原子的c面; 包括形成在沟道层上的AlGaN的电子给体层，其中：电子给体层的表面是Al或Ga原子的c个面; 形成在电子供体层上的源电极和漏电极; 形成在源电极和漏电极之间的包含GaN或InGaAlN的覆盖层，其中：覆盖层的表面是Ga或In原子的c面，并且覆盖层的至少一部分与电子给体层接触; 以及形成为至少一部分与盖层接触的栅电极。

公开(公告)号：US06924516B2

公开(公告)日：2005-08-02

申请号：US10711134

申请日：2004-08-26

申请人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

发明人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

IPC分类号： H01L29/04 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778 ,  H01L31/0328

CPC分类号： H01L29/7783 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/42316

摘要： A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer,wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.

摘要翻译： 半导体器件包括：衬底; 包括形成在衬底上的GaN的缓冲层，其中：缓冲层的表面是Ga原子的c个面; 在缓冲层上形成包括GaN或InGaN的沟道层，其中：沟道层的表面是Ga或In原子的c面; 包括形成在沟道层上的AlGaN的电子给体层，其中：电子给体层的表面是Al或Ga原子的c个面; 形成在电子供体层上的源电极和漏电极; 形成在源电极和漏电极之间的包含GaN或InGaAlN的覆盖层，其中：覆盖层的表面是Ga或In原子的c面，并且覆盖层的至少一部分与电子给体层接触; 以及形成为至少一部分与盖层接触的栅电极。

公开(公告)号：US06639255B2

公开(公告)日：2003-10-28

申请号：US09733593

申请日：2000-12-08

申请人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

发明人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

IPC分类号： H01L29737

CPC分类号： H01L29/7783 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/42316

摘要： A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.

摘要翻译： 半导体器件包括：衬底; 包括形成在衬底上的GaN的缓冲层，其中：缓冲层的表面是Ga原子的c个面; 在缓冲层上形成包括GaN或InGaN的沟道层，其中：沟道层的表面是Ga或In原子的c面; 包括形成在沟道层上的AlGaN的电子给体层，其中：电子给体层的表面是Al或Ga原子的c个面; 形成在电子供体层上的源电极和漏电极; 形成在源电极和漏电极之间的包含GaN或InGaAlN的覆盖层，其中：所述覆盖层的表面是Ga或In原子的c面，并且所述覆盖层的至少一部分与所述电子给体层接触; 以及形成为至少一部分与盖层接触的栅电极。