公开(公告)号：US20120257443A1

公开(公告)日：2012-10-11

申请号：US13528025

申请日：2012-06-20

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US08232589B2

公开(公告)日：2012-07-31

申请号：US13352142

申请日：2012-01-17

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L29/788 ,  H01L21/8242

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US20120113709A1

公开(公告)日：2012-05-10

申请号：US13352142

申请日：2012-01-17

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US08125017B2

公开(公告)日：2012-02-28

申请号：US13067177

申请日：2011-05-13

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L29/788 ,  H01L21/8242

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US07087942B2

公开(公告)日：2006-08-08

申请号：US11288287

申请日：2005-11-29

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L27/10 ,  H01L29/80 ,  H01L29/76

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储器电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US06885057B2

公开(公告)日：2005-04-26

申请号：US10158903

申请日：2002-06-03

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H03K19/00 ,  H01L29/788

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US06977858B2

公开(公告)日：2005-12-20

申请号：US10728965

申请日：2003-12-08

申请人： Kenichi Osada ,  Takayuki Kawahara ,  Ken Yamaguchi ,  Yoshikazu Saito ,  Naoki Kitai

发明人： Kenichi Osada ,  Takayuki Kawahara ,  Ken Yamaguchi ,  Yoshikazu Saito ,  Naoki Kitai

IPC分类号： G11C11/413 ,  G06F11/10 ,  G11C7/22 ,  G11C7/24 ,  G11C29/00 ,  G11C29/42 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  G11C7/00

CPC分类号： G06F11/1008 ,  G06F11/108 ,  G11C5/025 ,  G11C7/22 ,  G11C7/24 ,  G11C8/20 ,  G11C11/412 ,  G11C2207/2218 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/1104

摘要： A semiconductor device comprises, a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.

摘要翻译： 半导体器件包括多个存储器单元和纠错电路，其中通过后置写入方法进行写入操作，并且与写入并行执行ECC处理，从而缩短了周期时间。 此外，当存储单元通过阱抽头供电时，更好的是，当存储单元通过井口供电时，不分配相同的地址。

公开(公告)号：US07692943B2

公开(公告)日：2010-04-06

申请号：US12000135

申请日：2007-12-10

申请人： Kenichi Osada ,  Takayuki Kawahara ,  Ken Yamaguchi ,  Yoshikazu Saito ,  Naoki Kitai

发明人： Kenichi Osada ,  Takayuki Kawahara ,  Ken Yamaguchi ,  Yoshikazu Saito ,  Naoki Kitai

IPC分类号： G11C5/02

CPC分类号： G06F11/1008 ,  G06F11/108 ,  G11C5/025 ,  G11C7/22 ,  G11C7/24 ,  G11C8/20 ,  G11C11/412 ,  G11C2207/2218 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/1104

摘要： A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.

摘要翻译： 半导体器件包括多个存储单元和纠错电路。 其写入操作是通过后期写入方式进行的，并且与写入并行执行ECC处理以缩短周期时间。 此外，当存储单元通过阱抽头供电时，在存储单元通过井口供电时，不分配相同的地址。

公开(公告)号：US20060028853A1

公开(公告)日：2006-02-09

申请号：US11242054

申请日：2005-10-04

申请人： Kenichi Osada ,  Takayuki Kawahara ,  Ken Yamaguchi ,  Yoshikazu Saito ,  Naoki Kitai

发明人： Kenichi Osada ,  Takayuki Kawahara ,  Ken Yamaguchi ,  Yoshikazu Saito ,  Naoki Kitai

IPC分类号： G11C5/06 ,  G11C7/00

CPC分类号： G06F11/1008 ,  G06F11/108 ,  G11C5/025 ,  G11C7/22 ,  G11C7/24 ,  G11C8/20 ,  G11C11/412 ,  G11C2207/2218 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/1104

摘要： According to one aspect of the present invention, there is provided a semiconductor device comprising a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.

摘要翻译： 根据本发明的一个方面，提供了一种包括多个存储单元的半导体器件和一个纠错电路，其中写操作是通过后期写入方式执行的，ECC处理与写入并行执行 ，从而缩短周期时间。 此外，当存储单元通过阱抽头供电时，更好的是，当存储单元通过井口供电时，不分配相同的地址。

公开(公告)号：US20110128780A1

公开(公告)日：2011-06-02

申请号：US13024252

申请日：2011-02-09

申请人： Kenichi OSADA ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

发明人： Kenichi OSADA ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0092 ,  G11C2213/79

摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.

摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。