利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

38 条记录 (耗时 0.042 秒)

    Multi-dot flash memory and method of manufacturing the same
    13.
    发明授权
    Multi-dot flash memory and method of manufacturing the same 有权
    多点闪存及其制造方法

    公开(公告)号：US08456908B2

    公开(公告)日：2013-06-04

    申请号：US12563729

    申请日：2009-09-21

    申请人： Takashi Ichikawa ,  Hiroshi Watanabe ,  Kenji Kawabata

    发明人： Takashi Ichikawa ,  Hiroshi Watanabe ,  Kenji Kawabata

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  H01L29/788

    CPC分类号： H01L21/28132 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical.

    摘要翻译： 多点闪速存储器包括沿第一方向布置的有源区域，其延伸到与第一方向交叉的第二方向，第一和第二方向平行于半导体衬底的表面，沿第一方向布置的浮动栅极， 设置在有源区域之上，设置在浮动栅极上方的字线​​，其延伸到第一方向，以及设置在浮动栅极之间的位线，其延伸到第二方向。 每个浮动栅极具有在第一方向上的两个侧表面，两个侧表面的形状彼此不同，并且在第一方向上彼此相邻的浮置栅极的相对表面的形状是对称的。

    Semiconductor storage device and manufacturing method thereof
    14.
    发明授权
    Semiconductor storage device and manufacturing method thereof 有权
    半导体存储装置及其制造方法

    公开(公告)号：US08198665B2

    公开(公告)日：2012-06-12

    申请号：US12245396

    申请日：2008-10-03

    申请人： Kenji Kawabata ,  Hisataka Meguro

    发明人： Kenji Kawabata ,  Hisataka Meguro

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L21/84 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/1203 ,  H01L29/127 ,  H01L29/7888

    摘要： A semiconductor storage device includes: a substrate having a semiconductor layer at least on a surface thereof; and a plurality of quantum dot elements forming a charge storage layer formed above the semiconductor layer via a first insulating film that becomes a tunnel insulating film in such a manner that the quantum dot elements are connected with a bit line in series, wherein each quantum dot element forms a single electron memory.

    摘要翻译： 半导体存储装置包括：至少在其表面上具有半导体层的基板; 以及形成电荷存储层的多个量子点元件，其经由形成隧道绝缘膜的第一绝缘膜形成在半导体层上方，使得量子点元件与位线串联连接，其中每个量子点 元件形成单个电子存储器。

    Semiconductor storage element and manufacturing method thereof
    15.
    发明申请
    Semiconductor storage element and manufacturing method thereof 有权
    半导体存储元件及其制造方法

    公开(公告)号：US20110143503A1

    公开(公告)日：2011-06-16

    申请号：US12929843

    申请日：2011-02-18

    申请人： Kenji Kawabata

    发明人： Kenji Kawabata

    IPC分类号： H01L21/336 ,  H01L21/283

    CPC分类号： H01L27/1203 ,  H01L21/0334 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  Y10S977/936 ,  Y10S977/943

    摘要： A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.

    摘要翻译： 半导体存储元件包括：由在基板上形成的具有预定宽度的线图案构成的半导体层; 形成通过用作隧道绝缘膜的第一绝缘膜在半导体层上形成的电荷存储层的量子点; 形成在所述半导体层的表面层中以将所述量子点夹在其间的杂质扩散层; 以及通过第二绝缘膜形成在量子点上的控制电极。

    MULTI-DOT FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME
    16.
    发明申请
    MULTI-DOT FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME 有权
    多点闪存及其制造方法

    公开(公告)号：US20100214840A1

    公开(公告)日：2010-08-26

    申请号：US12563729

    申请日：2009-09-21

    申请人： Takashi Ichikawa ,  Hiroshi Watanabe ,  Kenji Kawabata

    发明人： Takashi Ichikawa ,  Hiroshi Watanabe ,  Kenji Kawabata

    IPC分类号： G11C16/04 ,  H01L21/336

    CPC分类号： H01L21/28132 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical.

    摘要翻译： 多点闪速存储器包括沿第一方向布置的有源区域，其延伸到与第一方向交叉的第二方向，第一和第二方向平行于半导体衬底的表面，沿第一方向布置的浮动栅极， 设置在有源区域之上，设置在浮动栅极上方的字线​​，其延伸到第一方向，以及设置在浮动栅极之间的位线，其延伸到第二方向。 每个浮动栅极具有在第一方向上的两个侧表面，两个侧表面的形状彼此不同，并且在第一方向上彼此相邻的浮置栅极的相对表面的形状是对称的。

    Apparatus and method of predicting performance of semiconductor manufacturing process and semiconductor device, and manufacturing method of semiconductor device
    18.
    发明申请
    Apparatus and method of predicting performance of semiconductor manufacturing process and semiconductor device, and manufacturing method of semiconductor device 审中-公开
    半导体制造工艺和半导体器件的性能预测装置及方法以及半导体器件的制造方法

    公开(公告)号：US20070042512A1

    公开(公告)日：2007-02-22

    申请号：US11504048

    申请日：2006-08-15

    申请人： Kenji Kawabata

    发明人： Kenji Kawabata

    IPC分类号： H01L21/66

    CPC分类号： G05B17/02

    摘要： Apparatus and method of predicting performance of a semiconductor manufacturing process and device, which reduces simulation resources to predict the performance distribution in the wafer and manufacturing method of a semiconductor device are disclosed. According to one aspect, it is provided a performance prediction apparatus comprising a uniform mesh data generator generating uniform mesh data by dividing a wafer using a uniform mesh to predict an in-plane characteristics distribution of performance in a series of process steps, a non-uniform mesh generator generating a non-uniform mesh by combining element meshes based on the uniform mesh data and predetermined threshold, a common mesh generator generating a common mesh by superimposing the non-uniform meshes and selecting a minimum mesh by region, a common mesh data generator generating common mesh data by representing the performance using the common mesh, and a predicting section predicting a comprehensive performance after processing the series of processes.

    摘要翻译： 公开了一种预测半导体制造工艺和器件的性能的装置和方法，其减少了模拟资源以预测晶片的性能分布以及半导体器件的制造方法。 根据一个方面，提供了一种性能预测装置，其包括均匀网格数据生成器，其通过使用均匀网格划分晶片来生成均匀网格数据，以预测一系列处理步骤中的平面性能分布特性， 均匀网格生成器通过基于均匀网格数据和预定阈值组合元素网格来生成不均匀网格;公共网格生成器，通过叠加非均匀网格并且逐区选择最小网格来生成公共网格，公共网格数据 发生器通过使用公共网格表示性能来生成公共网格数据，以及预测部分，其在处理一系列处理之后预测综合性能。

    Method for analyzing fail bit maps of waters and apparatus therefor
    19.
    发明授权
    Method for analyzing fail bit maps of waters and apparatus therefor 失效
    分析水域及其设备失效位图的方法

    公开(公告)号：US07405088B2

    公开(公告)日：2008-07-29

    申请号：US10801992

    申请日：2004-03-17

    申请人： Hiroshi Matsushita ,  Kenichi Kadota ,  Kenji Kawabata ,  Yoshiyuki Shioyama

    发明人： Hiroshi Matsushita ,  Kenichi Kadota ,  Kenji Kawabata ,  Yoshiyuki Shioyama

    IPC分类号： H01L21/00

    CPC分类号： H01L22/20

    摘要： A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.

    摘要翻译： 根据本发明的故障分析方法包括在输入设备的多个晶片中输入故障的位置; 准备多个晶片的多个部分; 计算特征量，其由表示多个晶片中的故障的分布的至少一个数值表示，用于多个部分中的每一个; 并且通过第一数值表示在特征量方面的多个晶片之间的相似度。 随后，该方法包括对于每个多个晶片检测具有大于预定第一阈值的第一数值的另一个晶片，并且形成具有类似故障分布的多个晶片的相似晶片组。