公开(公告)号：US20070212811A1

公开(公告)日：2007-09-13

申请号：US11788523

申请日：2007-04-19

申请人： Hiroji Hanawa ,  Kartik Ramaswamy ,  Kenneth Collins ,  Amir Al-Bayati ,  Biagio Gallo ,  Andrew Nguyen

发明人： Hiroji Hanawa ,  Kartik Ramaswamy ,  Kenneth Collins ,  Amir Al-Bayati ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01L21/16

CPC分类号： H01L21/02274 ,  C23C14/48 ,  C23C16/507 ,  H01J37/321 ,  H01J37/32174 ,  H01J37/32357 ,  H01J37/32412 ,  H01J2237/2001 ,  H01L21/02126 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659 ,  Y10T29/5313

摘要： Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low temperature CVD steps with a toroidal RF plasma current while applying an RF plasma bias voltage. The temperature of the workpiece is held below a threshold photoresist removal temperature. The RF bias voltage is held at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.

摘要翻译： 通过在每个N沟道和P沟道器件组中的每一个上对光阻单元进行连续掩蔽，同时在CMOS器件上沉积器件增强涂层，同时对另一个器件进行掩蔽或者脱离另一个器件，并且在每个步骤连续地掩蔽器件组中的一个器件 在施加RF等离子体偏压的同时，用环形RF等离子体电流进行低温CVD步骤。 工件的温度保持在阈值光刻胶去除温度以下。 当未屏蔽组由P沟道器件组成并且当未屏蔽组由N沟道器件组成时，RF偏置电压保持在第一应力下沉积涂层的水平。

公开(公告)号：US20070032095A1

公开(公告)日：2007-02-08

申请号：US11199572

申请日：2005-08-08

申请人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

发明人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

IPC分类号： H01L21/00

CPC分类号： B23K26/0738 ,  B23K26/0608 ,  B23K26/0876 ,  B23K26/361 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886

摘要： A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls, depositing a metal barrier layer comprising the barrier metal on the first barrier layer, depositing a main conductor species seed layer on the metal barrier layer and depositing a main conductor layer. The method further includes annealing the main conductor layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light. The method of Claim 1 further comprising, prior to the annealing step, depositing an amorphous carbon optical absorber layer on the main conductor layer. The step of depositing an amorphous carbon optical absorber layer includes introducing a carbon-containing process gas into a reactor chamber containing the substrate in a process zone of the reactor, applying RF source power to an external reentrant conduit of the reactor to generate a reentrant toroidal RF plasma current passing through the process zone and applying a bias voltage to the substrate.

摘要翻译： 在半导体衬底上形成薄膜结构中的导体的方法包括在具有垂直侧壁的基底层中形成高纵横比的开口，在高方面的表面上沉积包含阻挡金属的电介质化合物的介电阻挡层 比例开口，包括垂直侧壁，在第一阻挡层上沉积包括阻挡金属的金属阻挡层，在金属阻挡层上沉积主导体种子种子层并沉积主导体层。 该方法还包括通过以下步骤来退火主导体层：（a）将来自连续波激光器阵列的光引导到至少部分穿过薄膜结构的光线，以及（b）相对于薄的平面 薄膜结构在横向于光线的方向上。 2.根据权利要求1所述的方法，还包括在所述退火步骤之前，在所述主导体层上沉积无定形碳光吸收层。 沉积无定形碳光吸收层的步骤包括将含碳工艺气体引入反应器的反应器室中，该反应器室在反应器的工艺区域中，将RF源功率施加到反应器的外部折入导管以产生可重入环形 RF等离子体电流通过工艺区域并向衬底施加偏置电压。

公开(公告)号：US20070032054A1

公开(公告)日：2007-02-08

申请号：US11199593

申请日：2005-08-08

申请人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

发明人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

IPC分类号： H01L21/26

CPC分类号： H01L21/0276 ,  C23C16/26 ,  C23C16/507 ,  H01J37/321 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/268 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S430/151

摘要： A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern, and depositing a carbon-containing hard mask layer on the substrate by (a) introducing a carbon-containing process gas into the chamber, (b) generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, and (c) coupling RF plasma bias power or bias voltage to the workpiece. The method further includes photolithographically defining the predetermined pattern in the carbon-containing hard mask layer, and etching the target layer in the presence of the hard mask layer.

摘要翻译： 使用光学可写掩模在半导体衬底上处理薄膜结构的方法包括将衬底放置在反应室中，所述衬底在其表面上根据预定图案在其表面上具有待蚀刻的靶层，并且沉积碳 - （a）将含碳工艺气体引入所述腔室中，（b）在折入路径中产生可重入环形的RF等离子体电流，所述凹入的RF等离子体电流包括通过耦合等离子体RF源功率的工件区域 到（c）将RF等离子体偏置功率或偏置电压耦合到工件的外部部分。 该方法还包括光刻地限定含碳硬掩模层中的预定图案，并且在存在硬掩模层的情况下蚀刻目标层。

公开(公告)号：US20060088655A1

公开(公告)日：2006-04-27

申请号：US10971772

申请日：2004-10-23

申请人： Kenneth Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Amir Al-Bayati ,  Andrew Nguyen ,  Biagio Gallo

发明人： Kenneth Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Amir Al-Bayati ,  Andrew Nguyen ,  Biagio Gallo

IPC分类号： C23C14/00 ,  C23C16/52

CPC分类号： H01J37/321 ,  C23C14/48 ,  C23C14/54 ,  H01J37/32412 ,  H01J37/32935

摘要： A method of measuring ion dose in a plasma immersion ion implantation reactor during ion implantation of a selected species into a workpiece includes placing the workpiece on a pedestal in the reactor and feeding into the reactor a process gas comprising a species to be implanted into the workpiece, and then coupling RF plasma source power to a plasma in the reactor. It further includes coupling RF bias power to the workpiece by an RF bias power generator that is coupled to the workpiece through a bias feedpoint of the reactor and measuring RF current at the feedpoint to generate a current-related value, and then integrating the current-related over time to produce an ion implantation dose-related value.

摘要翻译： 在将所选择的物质离子注入工件期间测量等离子体浸入式离子注入反应器中的离子剂量的方法包括将工件放置在反应器中的基座上，并将反应器中的工件气体进料到反应器中， 然后将RF等离子体源功率耦合到反应器中的等离子体。 它还包括通过RF偏置功率发生器将RF偏置功率耦合到工件，该RF偏置功率发生器通过电抗器的偏置馈电点耦合到工件，并且在馈电点处测量RF电流以产生电流相关值， 随着时间的推移产生离子注入剂量相关值。

公开(公告)号：US20060073683A1

公开(公告)日：2006-04-06

申请号：US11284975

申请日：2005-11-21

申请人： Kenneth Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Amir Al-Bayati ,  Biagio Gallo ,  Gonzalo Monroy

发明人： Kenneth Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Amir Al-Bayati ,  Biagio Gallo ,  Gonzalo Monroy

IPC分类号： H01L21/04

CPC分类号： H01J37/32357 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/32412 ,  H01L21/2236

摘要： A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking voltage to the electrostatic chuck. The method further includes introducing into the chamber a precursor gas including a species to be ion implanted in the workpiece and applying an RF bias to the electrostatic chuck, the RF bias having a bias level corresponding to the ion implantation profile depth.

摘要翻译： 将工件中的物质离子注入到选定的离子注入轮廓深度的方法包括将具有半导体材料的工件放置在等离子体反应器室的处理区域中或其附近的静电卡盘上，并向静电卡盘施加夹持电压。 所述方法还包括将包括要离子植入的物质的前体气体引入所述室中并将RF偏压施加到所述静电卡盘，所述RF偏压具有对应于所述离子注入轮廓深度的偏置电平。

公开(公告)号：US20050191828A1

公开(公告)日：2005-09-01

申请号：US11003000

申请日：2004-12-01

申请人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01J37/32 ,  H01L21/4763

CPC分类号： H01J37/32082 ,  H01J37/321 ,  H01L21/76254

摘要： An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

摘要翻译： 集成的微电子电路具有覆盖由堆叠的金属图案层和分离相邻的所述金属图案层的绝缘层的晶体管的多层互连结构。 每个绝缘层是具有分布在电介质材料的体积内的多个气泡的介电材料，以降低材料的介电常数，气泡通过将气态物质离子注入电介质材料而形成。

公开(公告)号：US20070042580A1

公开(公告)日：2007-02-22

申请号：US11551196

申请日：2006-10-19

申请人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01L21/425

CPC分类号： H01L21/823864 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/823871 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

摘要翻译： 集成的微电子电路具有覆盖由堆叠的金属图案层和分离相邻的所述金属图案层的绝缘层的晶体管的多层互连结构。 每个绝缘层是具有分布在电介质材料的体积内的多个气泡的介电材料，以降低材料的介电常数，气泡通过将气态物质离子注入电介质材料而形成。

公开(公告)号：US20060263540A1

公开(公告)日：2006-11-23

申请号：US11131899

申请日：2005-05-17

申请人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

发明人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

IPC分类号： H05H1/24

CPC分类号： H05H1/46

摘要： A method of processing a workpiece includes introducing an optical absorber material precursor gas into a chamber containing the workpiece, generating an RF oscillating toroidal plasma current in a reentrant path that includes a process zone overlying the workpiece by applying RF source power, so as to deposit a layer of an optical absorber material on the workpiece, and exposing the workpiece to optical radiation that is at least partially absorbed in the optical absorber layer.

摘要翻译： 一种处理工件的方法包括将光吸收材料前体气体引入到包含工件的室中，在折入路径中产生RF振荡环形等离子体电流，其包括通过施加RF源功率覆盖工件的工艺区域，以便沉积 在工件上的光吸收材料层，以及将工件暴露于至少部分地吸收在光吸收层中的光辐射。

公开(公告)号：US20050136604A1

公开(公告)日：2005-06-23

申请号：US11002965

申请日：2004-12-01

申请人： Amir Al-Bayati ,  Kenneth Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Kenneth Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01J37/32 ,  H01L21/336

CPC分类号： H01J37/321 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/78618

摘要： A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into the transistor. Some embodiments employ both conformal ion implantation and conformal deposition of dopant containing films, and in those embodiments in which the dopant containing film is a pure dopant, the ion implantation and film deposition can be performed simultaneously.

摘要翻译： 通过绝缘体上半导体结构中的三维垂直晶体管的垂直和水平表面进行保形掺杂的工艺采用RF振荡环形等离子体电流来执行保形离子注入或含掺杂剂膜的共形沉积 然后可以加热以将掺杂剂驱动到晶体管中。 一些实施例采用包含掺杂剂的膜的共形离子注入和共形沉积，并且在其中含掺杂剂的膜是纯掺杂剂的那些实施例中，可以同时执行离子注入和膜沉积。

公开(公告)号：US20050070073A1

公开(公告)日：2005-03-31

申请号：US10989993

申请日：2004-11-16

申请人： Amir Al-Bayati ,  Kenneth Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Kenneth Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01J37/32 ,  H01L21/301

CPC分类号： H01L21/76254 ,  C23C14/48 ,  C23C16/507 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32412 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659

摘要： A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of a first species in the first surface of at least either of the pair of wafers. The method further includes performing a cleavage ion implantation step on one of the pair of wafers by ion implanting a second species to define a cleavage plane across a diameter of the wafer at the predetermined depth below the top surface of the one wafer. The wafers are then bonded together by placing the first surfaces of the pair of wafers onto one another so as to form an semiconductor-on-insulator structure. The method also includes separating the one wafer along the cleavage plane so as to remove a portion of the one wafer between the second surface and the cleavage plane, whereby to form an exposed cleaved surface of a remaining portion of the one wafer on the semiconductor-on-insulator structure. Finally, the cleaved surface is smoothed, preferably by carrying out a low energy high momentum ion implantation step.

摘要翻译： 一种从一对半导体晶片制造绝缘体上半导体结构的方法包括在第一晶片的至少第一表面上形成氧化物层，并通过离子注入第一种类进行接合增强注入步骤 在所述一对晶片中的至少一个的第一表面中。 所述方法还包括通过离子注入第二种类来在所述一对晶片之一上执行切割离子注入步骤，以在所述晶片的顶部表面下方的预定深度处限定跨所述晶片的直径的解理面。 然后通过将一对晶片的第一表面放置在彼此上而将晶片结合在一起，以形成绝缘体上半导体结构。 该方法还包括沿着解理平面分离一个晶片，以便去除第二表面和解理面之间的一个晶片的一部分，从而形成半导体芯片上的一个晶片的剩余部分的暴露的切割表面， 绝缘体上的结构。 最后，优选通过进行低能量的高动量离子注入步骤来平滑切割的表面。