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    Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device
    11.
    发明申请
    Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件和非易失性半导体存储器件中的编程方法

    公开(公告)号：US20050185470A1

    公开(公告)日：2005-08-25

    申请号：US11059382

    申请日：2005-02-17

    申请人： Junichi Suzuki ,  Kohji Kanamori

    发明人： Junichi Suzuki ,  Kohji Kanamori

    IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/3468 ,  G11C16/12

    摘要： A memory cell array includes a plurality of memory cells each of which has a control gate and a floating gate. A programming circuit operates in a first programming mode followed by a second programming mode. In the first programming mode, the programming circuit applies a first program pulse to first memory cells while progressively increasing a programming capability of the first program pulse until threshold voltages of the first memory cells become higher than or equal to a first reference voltage. In the second programming mode, the programming circuit applies a second program pulse to second memory cells included in the first memory cells and having threshold voltages lower than a second reference voltage that is higher than the first reference voltage until the threshold voltages of the second memory cells become higher than or equal to the second reference voltage.

    摘要翻译： 存储单元阵列包括多个存储单元，每个存储单元具有控制栅极和浮置栅极。 编程电路以第一编程模式工作，随后是第二编程模式。 在第一编程模式中，编程电路将第一编程脉冲施加到第一存储单元，同时逐渐增加第一编程脉冲的编程能力，直到第一存储单元的阈值电压变为高于或等于第一参考电压。 在第二编程模式中，编程电路将第二编程脉冲施加到包括在第一存储单元中的第二存储单元，并具有低于高于第一参考电压的第二参考电压的阈值电压，直到第二存储器的阈值电压 单元变得高于或等于第二参考电压。

    Semiconductor memory and manufacturing method thereof
    12.
    发明授权
    Semiconductor memory and manufacturing method thereof 失效
    半导体存储器及其制造方法

    公开(公告)号：US06414346B1

    公开(公告)日：2002-07-02

    申请号：US09767568

    申请日：2001-01-23

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： H01L27108

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A semiconductor memory is provided with a memory cell region and a peripheral circuit region. The memory cell region includes semiconductor memory cells arranged in an array and element separating shield electrodes. The element separating shield electrodes extend in a column direction and separate semiconductor memory cells being adjacent to each other in a row direction. Further, a peripheral circuit sending and receiving data to and from the semiconductor memory cell is provided in the peripheral circuit region. Elements in the peripheral circuit are separated by an element separation insulating film. The element separating shield electrodes extend onto the element separation insulating film at a boundary between the memory cell region and the peripheral circuit region.

    摘要翻译： 半导体存储器设置有存储单元区域和外围电路区域。 存储单元区域包括排列成阵列的半导体存储单元和隔离屏蔽电极的元件。 分离屏蔽电极的元件在列方向上延伸，并且在行方向上分离彼此相邻的半导体存储单元。 此外，在外围电路区域中提供向半导体存储单元发送数据和从半导体存储单元接收数据的外围电路。 外围电路中的元件由元件隔离绝缘膜分开。 分离屏蔽电极的元件在存储单元区域和外围电路区域之间的边界处延伸到元件隔离绝缘膜上。

    Semiconductor device with no step between well regions
    13.
    发明授权
    Semiconductor device with no step between well regions 失效
    半导体器件在阱区之间没有一步

    公开(公告)号：US06201274B1

    公开(公告)日：2001-03-13

    申请号：US09179392

    申请日：1998-10-27

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： H01L2976

    CPC分类号： H01L27/11526 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

    摘要： In a semiconductor device having a high voltage transistor, a first well region of the high voltage transistor is formed in a semiconductor substrate as a channel region. The first well region has a first conductive type. Second well regions of the high voltage transistor are formed in the semiconductor substrate as a source region and a drain region to sandwich the first well region. The second well region has a second conductive type. A surface of the first region and surfaces of the second well regions have a flat plane.

    摘要翻译： 在具有高电压晶体管的半导体器件中，高压晶体管的第一阱区形成在半导体衬底中作为沟道区。 第一阱区具有第一导电类型。 在半导体衬底中形成高压晶体管的第二阱区作为源极区和漏极区以夹持第一阱区。 第二阱区具有第二导电类型。 第一区域的表面和第二阱区域的表面具有平坦的平面。

    Method of making non-volatile semiconductor memory devices having large capacitance between floating and control gates
    14.
    发明授权
    Method of making non-volatile semiconductor memory devices having large capacitance between floating and control gates 失效
    制造在浮动栅极和控制栅极之间具有大电容的非易失性半导体存储器件的方法

    公开(公告)号：US5863822A

    公开(公告)日：1999-01-26

    申请号：US796597

    申请日：1997-02-07

    申请人： Kohji Kanamori ,  Yosiaki Hisamune

    发明人： Kohji Kanamori ,  Yosiaki Hisamune

    IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/42324 ,  H01L29/66825 ,  Y10S438/981

    摘要： Disclosed herein is a stacked gate type non-volatile semiconductor memory cell including source/drain regions having a first portion covered with a tunnel oxide film and a second portion covered with an insulator film. The memory cell further includes a gate insulating film formed on a channel region, wherein the tunnel insulating film is thinner than the gate oxide film and the insulator film is thicker than the gate insulating film. A floating gate is formed on the respective insulating films and a control gate is formed over the floating gate with an intervention of a second gate insulating film.

    摘要翻译： 本文公开了一种堆叠栅极型非易失性半导体存储单元，其包括具有覆盖有隧道氧化物膜的第一部分和覆盖有绝缘膜的第二部分的源极/漏极区域。 存储单元还包括形成在沟道区上的栅极绝缘膜，其中隧道绝缘膜比栅极氧化膜薄，并且绝缘膜比栅极绝缘膜厚。 在各个绝缘膜上形成浮栅，并且在第二栅极绝缘膜的介入上在浮栅上方形成控制栅极。

    Nonvolatile semiconductor device and method of manufacturing same
    15.
    发明授权
    Nonvolatile semiconductor device and method of manufacturing same 失效
    非易失性半导体器件及其制造方法

    公开(公告)号：US5838611A

    公开(公告)日：1998-11-17

    申请号：US911002

    申请日：1997-08-14

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115

    摘要： A semiconductor memory device with a contactless array structure has bit-lines formed in a semiconductor substrate by diffusion of an impurity. Word-lines (control gates) are formed on the substrate so as to intersect the bit-lines. Floating gates are disposed in intersecting regions between the bit- and word-lines. Regions of higher resistance extend in parallel to the bit-lines located on both sides of a floating gates and located in an offset manner relative to the floating gate. A thick dielectric film is formed between the regions of higher resistance and word-lines. In this semiconductor memory device, a source side injection method with higher efficiency can be utilized for electron injection to a floating gate (programming) and thereby a lower programming voltage, less power consumption, and higher degree of integration are achieved.

    摘要翻译： 具有非接触阵列结构的半导体存储器件通过杂质的扩散在半导体衬底中形成位线。 字线（控制栅极）形成在基板上以与位线相交。 浮动栅极位于位线和字线之间的交叉区域。 较高电阻的区域平行于位于浮动栅极两侧的位线并且相对于浮动栅极以偏移方式定位。 在较高电阻和字线的区域之间形成厚电介质膜。 在该半导体存储器件中，可以利用具有更高效率的源极侧注入方法用于向浮动栅极（编程）的电子注入，从而实现较低的编程电压，更低的功率消耗和更高的集成度。

    Memory device
    16.
    发明授权
    Memory device 有权

    公开(公告)号：US10134752B2

    公开(公告)日：2018-11-20

    申请号：US15393775

    申请日：2016-12-29

    申请人： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

    发明人： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

    IPC分类号： H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  G11C16/04

    摘要： A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

    Semiconductor device and its manufacturing method
    18.
    发明授权
    Semiconductor device and its manufacturing method 有权
    半导体器件及其制造方法

    公开(公告)号：US07439602B2

    公开(公告)日：2008-10-21

    申请号：US10915773

    申请日：2004-08-11

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/76202 ,  H01L21/76224 ,  H01L27/115

    摘要： A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate oxide film (30). The active gate film (2) may be located in a central portion under of a gate electrode (3). The gate oxide film (30) may be located under end portions of the gate electrode (3). In this way, a distance between a shoulder portion of a trench (11) and a gate electrode (3) may be increased. Thus, an electric field concentration in the shoulder portion of the trench (11) may be decreased and memory cell characteristics may be improved.

    摘要翻译： 已经公开了一种半导体器件，其包括由可以与堆叠的膜图案（7）自对准的沟槽隔离的存储器单元。 存储单元可以是具有可以比栅极氧化膜（30）薄的有源栅极膜（2）的闪存单元。 有源栅极膜（2）可以位于栅电极（3）下方的中心部分。 栅极氧化膜（30）可以位于栅电极（3）的端部下方。 以这种方式，可以增加沟槽（11）的肩部与栅电极（3）之间的距离。 因此，可以减小沟槽（11）的肩部中的电场集中，并且可以提高存储单元特性。

    Semiconductor memory device
    19.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20080048248A1

    公开(公告)日：2008-02-28

    申请号：US11892278

    申请日：2007-08-21

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/42352 ,  H01L29/66833

    摘要： Provided is a highly reliable multi-bit memory cell capable of miniaturization including: a semiconductor substrate with a channel formed therein; diffusion layers arranged at two sides of the channel, for serving as source/drain; an insulating film arranged on a part of the channel; a trap film made of an insulating material having an electron trapping characteristic, arranged on the semiconductor substrate, the diffusion layers and the insulating film, and including trap regions each capable of trapping electrons in at least areas in contact with the semiconductor substrate at two sides of the insulating film; and a gate electrode arranged on the trap film. The trap regions are also formed on side surfaces of the insulating film, and the trap film has a structure in which the trap film is bent upward from the surface of the semiconductor substrate in the trap regions due to the insulating film.

    摘要翻译： 提供了一种能够小型化的高度可靠的多位存储单元，包括：其中形成有沟道的半导体衬底; 扩散层布置在通道的两侧，用作源极/漏极; 布置在所述通道的一部分上的绝缘膜; 由绝缘材料制成的具有电子俘获特性的陷阱膜，布置在半导体衬底上，扩散层和绝缘膜上，并且包括陷阱区，每个俘获区能够在至少与半导体衬底的两侧接触的区域中俘获电子 的绝缘膜; 以及布置在捕获膜上的栅电极。 捕获区也形成在绝缘膜的侧表面上，并且陷阱膜具有其中陷阱膜由于绝缘膜而从陷阱区域中的半导体衬底的表面向上弯曲的结构。