公开(公告)号：US5786607A

公开(公告)日：1998-07-28

申请号：US654962

申请日：1996-05-29

申请人： Katsuya Ishikawa ,  Takao Kuroda ,  Yuji Matsuda ,  Masahiko Niwayama ,  Keishi Tachikawa

发明人： Katsuya Ishikawa ,  Takao Kuroda ,  Yuji Matsuda ,  Masahiko Niwayama ,  Keishi Tachikawa

IPC分类号： H01L27/148 ,  H01L29/768

CPC分类号： H01L27/14812 ,  H01L27/14825

摘要： A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.

公开(公告)号：US08754422B2

公开(公告)日：2014-06-17

申请号：US13503172

申请日：2010-10-19

申请人： Chiaki Kudou ,  Kenya Yamashita ,  Masahiko Niwayama

发明人： Chiaki Kudou ,  Kenya Yamashita ,  Masahiko Niwayama

IPC分类号： H01L29/78

CPC分类号： H01L29/7828 ,  H01L21/0465 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device 100 includes: a first silicon carbide layer 120 arranged on the principal surface of a semiconductor substrate 101; a first impurity region 103 of a first conductivity type arranged in the first silicon carbide layer; a body region 104 of a second conductivity type; a contact region 131 of the second conductivity type which is arranged at a position in the body region that is deeper than the first impurity region 103 and which contains an impurity of the second conductivity type at a higher concentration than the body region; a drift region 102 of the first conductivity type; and a first ohmic electrode 122 in ohmic contact with the first impurity region 103 and the contact region 131, wherein: a contact trench 121, which penetrates through the first impurity region 103, is provided in the first silicon carbide layer 120; and the first ohmic electrode 122 is arranged in the contact trench 121 and is in contact with the contact region 131 on at least a portion of a side wall lower portion 121cL and a bottom surface 121b of the contact trench.

摘要翻译： 半导体器件100包括：布置在半导体衬底101的主表面上的第一碳化硅层120; 布置在第一碳化硅层中的第一导电类型的第一杂质区域103; 第二导电类型的体区104; 所述第二导电类型的接触区域131布置在比所述第一杂质区域103更深的所述体区域中并且包含比所述体区域更高的浓度的所述第二导电类型的杂质的位置处; 第一导电类型的漂移区域102; 以及与第一杂质区域103和接触区域131欧姆接触的第一欧姆电极122，其中：穿过第一杂质区域103的接触沟槽121设置在第一碳化硅层120中; 并且第一欧姆电极122布置在接触沟槽121中并且在接触沟槽的侧壁下部121cL和底表面121b的至少一部分上与接触区域131接触。

公开(公告)号：US07851871B2

公开(公告)日：2010-12-14

申请号：US12242142

申请日：2008-09-30

申请人： Yuji Harada ,  Kazuyuki Sawada ,  Masahiko Niwayama ,  Masaaki Okita

发明人： Yuji Harada ,  Kazuyuki Sawada ,  Masahiko Niwayama ,  Masaaki Okita

IPC分类号： H01L29/768

CPC分类号： H01L21/823462 ,  H01L21/823418

摘要： A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region; and a high concentration source region of a second conductivity type having a diffusion depth deeper than that of the low concentration source region. A diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET.

摘要翻译： 在第一导电型半导体基板上一起设置高压晶体管和包括第二导电型MOSFET的外围电路。 高电压晶体管包括：形成在半导体衬底中的第二导电类型的低浓度漏极区域; 形成在半导体衬底中并与低浓度漏极区隔开的第二导电类型的低浓度源区; 以及具有比低浓度源区域的扩散深度更深的扩散深度的第二导电类型的高浓度源区域。 低浓度源极区域的扩散深度等于MOSFET的源极/漏极区域的扩散深度。

公开(公告)号：US20080166822A1

公开(公告)日：2008-07-10

申请号：US11905227

申请日：2007-09-28

申请人： Masahiko Niwayama ,  Kenji Yoneda

发明人： Masahiko Niwayama ,  Kenji Yoneda

IPC分类号： H01L21/425

CPC分类号： H01J37/3171 ,  H01J37/026 ,  H01J37/304 ,  H01J2237/24535 ,  H01J2237/30472 ,  H01L21/28035

摘要： A semiconductor manufacturing apparatus includes: an ion source and a beam line for introducing an ion beam into a target film which is formed over a wafer with an insulating film interposed therebetween; a flood gun for supplying the target film with electrons for neutralizing charges contained in the ion beam; a rotating disk for subjecting the target film to mechanical scanning of the ion beam in two directions composed of r-θ directions; a rear Faraday cage for measuring the current density produced by the ion beam; a disk-rotational-speed controller and a disk-scanning-speed controller for changing the scanning speed of the target film; and a beam current/current density measuring instrument for controlling, according to the current density, the scanning speed of the target film.

摘要翻译： 一种半导体制造装置，包括：离子源和用于将离子束引入到晶片之间的绝缘膜之间形成的靶膜的离子束; 用于向目标膜提供用于中和离子束中的电荷的电子的洪水枪; 旋转盘，用于使目标膜在由θ-θ方向组成的两个方向上对离子束进行机械扫描; 用于测量由离子束产生的电流密度的后法拉第笼; 盘转速控制器和用于改变目标膜的扫描速度的盘扫描速度控制器; 以及用于根据电流密度控制目标膜的扫描速度的束电流/电流密度测量仪器。

公开(公告)号：US06633047B2

公开(公告)日：2003-10-14

申请号：US10184939

申请日：2002-07-01

申请人： Masahiko Niwayama ,  Hiroko Kubo ,  Kenji Yoneda

发明人： Masahiko Niwayama ,  Hiroko Kubo ,  Kenji Yoneda

IPC分类号： H01J37317

CPC分类号： H01L21/265 ,  H01J37/3171 ,  H01J2237/004 ,  H01J2237/31701 ,  H01L21/26513

摘要： An impurity introducing apparatus of the present invention includes: a system for introducing an impurity having charges into a target to be processed, the target being a semiconductor substrate or a film formed on the substrate; a system for supplying electrons into the target, the electrons canceling the charges of the impurity; and a system for controlling the maximum energy of the electrons supplied by the electron supply system at a predetermined value or less.

摘要翻译： 本发明的杂质导入装置包括：将具有电荷的杂质引入被处理对象物，所述靶为半导体基板或形成在所述基板上的膜的系统; 用于向目标物质供给电子的系统，电子消除杂质的电荷; 以及用于控制由电子供给系统提供的电子的最大能量以预定值或更小的系统。

公开(公告)号：US6046069A

公开(公告)日：2000-04-04

申请号：US796887

申请日：1997-02-05

申请人： Katsuya Ishikawa ,  Takao Kuroda ,  Yuji Matsuda ,  Masahiko Niwayama ,  Keishi Tachikawa

发明人： Katsuya Ishikawa ,  Takao Kuroda ,  Yuji Matsuda ,  Masahiko Niwayama ,  Keishi Tachikawa

IPC分类号： H01L27/148 ,  H01L21/00 ,  H01L21/339

CPC分类号： H01L27/14812 ,  H01L27/14825

摘要： A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.

摘要翻译： 具有如下结构的固体摄像装置，即使像素部分变得更细，在垂直CCD部分中转印电荷量也不会减少的结构，以及制造固态图像拾取装置的方法 被提供。 在N（100）硅衬底上形成第一p型阱和第二p型阱。 在第二p型阱3中形成垂直CCD n +层。然后，将杂质离子注入到包括垂直CCD n +层的上层部分的N（100）硅衬底的表面层中， 层。 与垂直CCD n +层隔离光电二极管部分的隔离部分和用于控制从光电二极管n层读取电荷的读取控制部分同时形成在与垂直CCD n +层相邻的部分上。

公开(公告)号：US07638782B2

公开(公告)日：2009-12-29

申请号：US11204050

申请日：2005-08-16

申请人： Kenji Yoneda ,  Masahiko Niwayama

发明人： Kenji Yoneda ,  Masahiko Niwayama

IPC分类号： G01K1/08 ,  H01J3/14 ,  H01J3/26

CPC分类号： H01J37/3171 ,  H01J37/3023 ,  H01J2237/0044 ,  H01J2237/043

摘要： Impurity ions are implanted into a semiconductor wafer of which a capacitor insulting film is formed on a principal face. In this impurity ion implantation step, the impurity ions are implanted into the semiconductor wafer in the form of a pulsed beam that repeats ON-OFF operation intermittently.

摘要翻译： 将杂质离子注入到在主面上形成电容器绝缘膜的半导体晶片中。 在这种杂质离子注入步骤中，杂质离子以间断地重复开 - 关操作的脉冲束的形式注入半导体晶片。

公开(公告)号：US20050130382A1

公开(公告)日：2005-06-16

申请号：US11000209

申请日：2004-12-01

申请人： Masahiko Niwayama ,  Kenji Yoneda ,  Kazuma Takahashi

发明人： Masahiko Niwayama ,  Kenji Yoneda ,  Kazuma Takahashi

IPC分类号： H01L21/265 ,  C23C16/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/045 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device includes the steps of: forming a semiconductor region of a first conductive type on a semiconductor wafer; forming a gate electrode on the semiconductor region; on the semiconductor region, forming a first insulating film over the whole surface including the upper surface of the gate electrode; by removing the formed first insulating film through etching from the top surface side; forming first sidewalls, covering the side surfaces of the gate electrode, from the first insulating film; and by implanting first impurity ions of a second conductive type to the semiconductor region by using an ion implantation device capable of processing a plurality of semiconductor wafers collectively, forming first impurity diffusion regions on both sides of the gate electrode in the semiconductor region; In the step of forming the first impurity diffusion regions, implantation of the first impurity ions are dividedly performed a plurality of times, and the semiconductor wafer is rotated in its wafer surface for each ion implantation.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体晶片上形成第一导电类型的半导体区域; 在所述半导体区域上形成栅电极; 在所述半导体区域上，在包括所述栅电极的上表面的整个表面上形成第一绝缘膜; 通过从上表面侧的蚀刻去除形成的第一绝缘膜; 从所述第一绝缘膜形成覆盖所述栅电极的侧表面的第一侧壁; 并且通过使用能够共同处理多个半导体晶片的离子注入装置将第二导电类型的第一杂质离子注入半导体区域，在半导体区域中的栅电极的两侧形成第一杂质扩散区; 在形成第一杂质扩散区域的步骤中，分散地进行第一杂质离子的注入多次，并且半导体晶片在其晶片表面中进行每次离子注入。

公开(公告)号：US06451674B1

公开(公告)日：2002-09-17

申请号：US09243797

申请日：1999-02-03

申请人： Masahiko Niwayama ,  Hiroko Kubo ,  Kenji Yoneda

发明人： Masahiko Niwayama ,  Hiroko Kubo ,  Kenji Yoneda

IPC分类号： H01L21425

CPC分类号： H01L21/265 ,  H01J37/3171 ,  H01J2237/004 ,  H01J2237/31701 ,  H01L21/26513

摘要： A method for introducing an impurity includes the steps of: introducing an impurity having charges into a target to be processed, such as a semiconductor substrate and a film formed on a substrate; and supplying electrons from a filament into the target to neutralize the charges of the impurity. The step of supplying electrons includes a step of controlling the maximum energy of the electrons supplied at a predetermined energy or less.

摘要翻译： 引入杂质的方法包括以下步骤：将具有电荷的杂质引入诸如半导体衬底的被处理靶和形成在衬底上的膜; 并将电子从灯丝提供到靶中以中和杂质的电荷。 提供电子的步骤包括控制以预定能量或更少能量供应的电子的最大能量的步骤。

公开(公告)号：US6025210A

公开(公告)日：2000-02-15

申请号：US900846

申请日：1997-07-25

申请人： Yuji Matsuda ,  Masahiko Niwayama

发明人： Yuji Matsuda ,  Masahiko Niwayama

IPC分类号： H01L27/148 ,  H01L21/00

CPC分类号： H01L27/14887

摘要： A solid-state imaging device provided here comprises a p-type semiconductor substrate, a p-type impurity layer formed thereon, a light-intercepting part formed inside said impurity layer for storing signal charges produced through incident light, and a n-type drain part formed in a region of the substrate excluding the light-intercepting part for discharging excess charges of the light-intercepting part. As a result, sensitivity characteristics on the long wavelength side can be improved, and miniaturization can be facilitated. An n-type buried drain part for discharging charges is formed under a transfer part via a p-type impurity layer. The readout side between the light-intercepting part and the transfer part is separated by a p-type readout control part which is installed to control threshold voltage (Vt), and the non-readout side is separated by a channel stopper. An insulating film is formed on the light-intercepting part and on the transfer part, and charges of the light-intercepting part are read out to the transfer part by the conductive-type electrode. For preventing dark current from arising, a p-type buried diffusion layer is formed at the interface of the light-intercepting part and the insulating film.

摘要翻译： 这里提供的固态成像装置包括p型半导体衬底，形成在其上的p型杂质层，形成在所述杂质层内部的用于存储通过入射光产生的信号电荷的遮光部分，以及n型漏极 部分形成在除了遮光部分之外的基板的区域中，用于排出遮光部分的多余电荷。 结果，能够提高长波长侧的灵敏度特性，能够实现小型化。 用于放电的n型埋漏部分经由p型杂质层形成在转印部分下面。 被遮光部分和转印部分之间的读出侧被安装成用于控制阈值电压（Vt）的p型读出控制部分分开，非读出侧被通道阻挡器分开。 在遮光部分和转印部分上形成绝缘膜，并且通过导电型电极将受光部分的电荷读出到转印部分。 为了防止产生暗电流，在遮光部分和绝缘膜的界面处形成p型掩埋扩散层。