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    NON-UNIFORM CHANNEL JUNCTION-LESS TRANSISTOR
    12.
    发明申请
    NON-UNIFORM CHANNEL JUNCTION-LESS TRANSISTOR 有权
    非均匀通道不连接晶体管

    公开(公告)号：US20120187486A1

    公开(公告)日：2012-07-26

    申请号：US13077144

    申请日：2011-03-31

    申请人： Ken-Ichi Goto ,  Zhiqiang Wu

    发明人： Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/66803 ,  G01N33/6893 ,  H01L29/785 ,  H01L2029/7857

    摘要： The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

    摘要翻译： 本公开公开了一种在衬底上形成半导体层的方法。 该方法包括将半导体层图案化成翅片结构。 该方法包括在鳍结构上形成栅介电层和栅电极层。 该方法包括以栅极结构缠绕翅片结构的一部分的方式构图栅极电介质层和栅极电极层以形成栅极结构。 该方法包括执行多个注入工艺以在散热片结构中形成源极/漏极区域。 多个注入工艺以这样一种方式进行，使得跨鳍片结构的掺杂分布不均匀，鳍结构部分被栅极结构缠绕的部分的第一区域具有较低的掺杂浓度水平 比其他地区的鳍结构。

    Non-uniform channel junction-less transistor
    15.
    发明授权
    Non-uniform channel junction-less transistor 有权
    不均匀沟道无结晶体管

    公开(公告)号：US08487378B2

    公开(公告)日：2013-07-16

    申请号：US13077144

    申请日：2011-03-31

    申请人： Ken-Ichi Goto ,  Zhiqiang Wu

    发明人： Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L27/12

    CPC分类号： H01L29/66803 ,  G01N33/6893 ,  H01L29/785 ,  H01L2029/7857

    摘要： The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

    摘要翻译： 本公开公开了一种在衬底上形成半导体层的方法。 该方法包括将半导体层图案化成翅片结构。 该方法包括在鳍结构上形成栅介电层和栅电极层。 该方法包括以栅极结构缠绕翅片结构的一部分的方式构图栅极电介质层和栅极电极层以形成栅极结构。 该方法包括执行多个注入工艺以在散热片结构中形成源极/漏极区域。 多个注入工艺以这样一种方式进行，使得跨鳍片结构的掺杂分布不均匀，鳍结构部分被栅极结构缠绕的部分的第一区域具有较低的掺杂浓度水平 比其他地区的鳍结构。

    SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE
    16.
    发明申请
    SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE 有权
    具有优化的DOPANT轮廓的半导体晶体管器件

    公开(公告)号：US20130113041A1

    公开(公告)日：2013-05-09

    申请号：US13288201

    申请日：2011-11-03

    申请人： Chia-Wen LIU ,  Tsung-Hsing Yu ,  Dhanyakumar Mahaveer Sathaiya ,  Wei-Hao Wu ,  Ken-Ichi Goto ,  Tzer-Min Shen ,  Zhiqiang Wu

    发明人： Chia-Wen LIU ,  Tsung-Hsing Yu ,  Dhanyakumar Mahaveer Sathaiya ,  Wei-Hao Wu ,  Ken-Ichi Goto ,  Tzer-Min Shen ,  Zhiqiang Wu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66492 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/931

    摘要： Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.

    摘要翻译： 提供了一种用于在半导体器件中形成晶体管的晶体管和方法。 该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。 使用具有非常低的倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。 如此形成的晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。 掺杂物分布还包括在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域的晶体管沟道。

    LOCAL CHARGE AND WORK FUNCTION ENGINEERING ON MOSFET
    18.
    发明申请
    LOCAL CHARGE AND WORK FUNCTION ENGINEERING ON MOSFET 有权
    MOSFET上的本地充电和工作功能工程

    公开(公告)号：US20100065925A1

    公开(公告)日：2010-03-18

    申请号：US12424170

    申请日：2009-04-15

    申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

    发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

    摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

    摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

    MOS devices with graded spacers and graded source/drain regions
    19.
    发明申请
    MOS devices with graded spacers and graded source/drain regions 审中-公开
    具有分级隔离器和分级源极/漏极区域的MOS器件

    公开(公告)号：US20080061379A1

    公开(公告)日：2008-03-13

    申请号：US11518046

    申请日：2006-09-08

    申请人： Hao-Yu Chen ,  Shui-Ming Cheng ,  Ken-Ichi Goto

    发明人： Hao-Yu Chen ,  Shui-Ming Cheng ,  Ken-Ichi Goto

    IPC分类号： H01L29/772

    CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： An MOS device includes a gate stack overlying a semiconductor substrate and a graded source/drain region adjacent to the gate stack. The graded source/drain region includes a first grade having a first depth, a second grade spaced further apart from a channel region than the first grade, and a third grade spaced further apart from the channel region than the second grade. The depth of the second grade is between the respective depths of the first and the third grades. The MOS device further includes a silicide region on a top surface of the source/drain region wherein the silicide region has an inner edge substantially aligned with an inner edge of the third grade, and a graded gate spacer comprising an inner portion on a sidewall of the gate stack and an outer portion on a sidewall of the inner portion.

    摘要翻译： MOS器件包括覆盖半导体衬底的栅极堆叠和与栅极堆叠相邻的渐变源极/漏极区域。 分级源极/漏极区域包括具有第一深度的第一等级，与沟道区间比第一等级更远离的第二等级，以及与第二等级相比更远离沟道区的三级。 二年级的深度在第一和第三等级的相应深度之间。 MOS器件还包括在源极/漏极区域的顶表面上的硅化物区域，其中硅化物区域具有基本上与三级内部边缘对准的内边缘，以及梯度栅极间隔件，其包括在侧壁上的内部部分 栅极堆叠和内部部分的侧壁上的外部部分。

    SOI transistors with improved source/drain structures with enhanced strain
    20.
    发明授权
    SOI transistors with improved source/drain structures with enhanced strain 有权
    具有改善的源/漏结构的SOI晶体管具有增强的应变

    公开(公告)号：US09263345B2

    公开(公告)日：2016-02-16

    申请号：US13451696

    申请日：2012-04-20

    申请人： Ken-Ichi Goto ,  Dhanyakumar Mahaveer Sathaiya ,  Ching-Chang Wu ,  Tzer-Min Shen

    发明人： Ken-Ichi Goto ,  Dhanyakumar Mahaveer Sathaiya ,  Ching-Chang Wu ,  Tzer-Min Shen

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L29/66 ,  H01L27/12 ,  H01L29/165 ,  H01L21/38

    CPC分类号： H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    摘要： A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance.

    摘要翻译： 提供了具有改进的器件性能的晶体管结构及其形成方法。 晶体管结构是SOI（绝缘体上硅）晶体管。 在一个实施例中，氧化物层上的硅层是相对均匀的膜，在另一个实施例中，氧化物层上的硅层是硅片。 晶体管器件包括由延伸穿过硅层的应变材料形成的源极/漏极结构，穿过氧化物层并进入可能是硅的下面的衬底。 源极/漏极结构还包括在硅层的上表面上方延伸的部分，从而提供增加的应变层的体积以提供附加的载流子迁移率和更高的性能。