利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

56 条记录 (耗时 0.036 秒)

    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS
    15.
    发明申请
    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS 有权
    用于控制集成电路中静态功耗的三端子开关

    公开(公告)号：US20090315010A1

    公开(公告)日：2009-12-24

    申请号：US12551631

    申请日：2009-09-01

    申请人： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    发明人： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    摘要： A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.

    摘要翻译： 一种用于集成电路装置的三端开关装置，包括设置在第一端子和第二端子之间的相变材料（PCM）; 加热装置，其设置在所述第二端子和第三端子之间的直接电接触中，所述加热装置位于所述PCM附近，并且被配置为将所述PCM的可变形部分的电导率切换到较低电阻结晶状态和较高电阻无定形状态 ; 以及绝缘层，其被配置为将所述加热器与所述PCM材料电隔离，并且所述加热器从所述第一端子电隔离。

    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS
    16.
    发明申请
    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS 有权
    用于控制集成电路中静态功耗的三端子开关

    公开(公告)号：US20080210925A1

    公开(公告)日：2008-09-04

    申请号：US12122969

    申请日：2008-05-19

    申请人： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    发明人： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    摘要： A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

    摘要翻译： 配置成用于控制集成电路中的静态功耗的开关电路包括连接在电压源端子和集成电路逻辑的对应子块之间的多个三端子相变材料（PCM）开关器件。 每个PCM开关装置还包括设置在第一端子和第二端子之间接触的PCM，在第二端子和第三端子之间接触地设置的加热装置，加热装置位于PCM附近，并且被配置为将 PCM的可变形部分的电导率在较低电阻结晶状态和较高电阻无定形状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。 第一个PCM开关器件的第三个端子耦合到一个设置/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

    Integrated circuit planarization and fill biasing design method
    17.
    发明授权
    Integrated circuit planarization and fill biasing design method 有权
    集成电路平面化和填充偏置设计方法

    公开(公告)号：US6121078A

    公开(公告)日：2000-09-19

    申请号：US154652

    申请日：1998-09-17

    申请人： John K. DeBrosse ,  Matthew R. Wordeman

    发明人： John K. DeBrosse ,  Matthew R. Wordeman

    IPC分类号： H01L21/762 ,  H01L21/82 ,  H01L27/06 ,  H01L21/338

    CPC分类号： H01L21/76224 ,  H01L21/82 ,  H01L27/0629

    摘要： An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the underlying well. The method may further comprise generating an active area (AA) dummy shape underlying the GC dummy shape. Biasing may be to the same voltage as the underlying well, or may be to a different voltage to create a decoupling capacitor. The biasing may be accomplished by implanting a well contact on an active area shape, the contact being N+ over an N-well or P+ over a P-well.

    摘要翻译： 一种用于集成电路芯片和芯片设计的隔离栅极平面化方法。 该方法包括产生虚拟栅极导体（GC）形状并将其偏压到下面的阱。 该方法还可以包括生成下面的GC虚拟形状的有源区（AA）虚拟形状。 偏置可能与下面的阱具有相同的电压，或者可以是不同的电压以产生去耦电容器。 偏置可以通过在有源区域形状上注入阱接触来实现，该触点是通过P阱的N阱或P +上的N +。

    Super low-power generator system for embedded applications
    20.
    发明授权
    Super low-power generator system for embedded applications 有权
    用于嵌入式应用的超低功耗发电机系统

    公开(公告)号：US06343044B1

    公开(公告)日：2002-01-29

    申请号：US09679124

    申请日：2000-10-04

    申请人： Louis Lu-Chen Hsu ,  Richard Michael Parent ,  Matthew R. Wordeman

    发明人： Louis Lu-Chen Hsu ,  Richard Michael Parent ,  Matthew R. Wordeman

    IPC分类号： G11C700

    CPC分类号： G11C11/406 ,  G11C5/146 ,  G11C8/08 ,  G11C11/4074 ,  G11C2207/104

    摘要： A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

    摘要翻译： 用于实现Vbb（阵列体偏置）和Vwl（负字线）电压发生器的存储电路中的功耗的显着降低的系统和方法。 该系统包括在睡眠或待机模式期间关闭负WL发生器，使得不消耗电力。 执行松弛的刷新操作，负的WL由Vbb发生器供电。 由于联合Vbb-Vwl去耦方案，耦合到BL摆幅的负WL电源的噪声减小。 在活动模式下，Vbb和Vneg被分离，以避免任何交叉噪声并保持设计灵活性。 在上电期间，Vwl发生器提高了Vbb电平的上升速率。 其优点可概括为：（1）Vbb发电机设计更简单，（2）Vbb发电机尺寸小得多，（3）Vbb功率降低，（4）Vwl发电机无待机电流，（5）低去耦噪声 待机或休眠模式下的Vwl电平，（6）上电期间Vbb的提升速率，（7）在活动模式期间Vbb和Vwl之间没有交叉噪声，（8）Vbb和Vbb的设计灵活性 Vwl处于活动模式。 本发明的原理和优点可以应用于任何两个或多个DC发电机系统，负极或正极。