公开(公告)号：US08482052B2

公开(公告)日：2013-07-09

申请号：US12056489

申请日：2008-03-27

Applicant: Hang-Ting Lue ,  Erh-Kun Lai

Inventor： Hang-Ting Lue ,  Erh-Kun Lai

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

Abstract: Thin film transistor memory cells are stackable, and employ bandgap engineered tunneling layers in a junction free, NAND configuration, that can be arranged in 3D arrays. The memory cells have a channel region in a semiconductor strip formed on an insulating layer, a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region, a charge storage layer disposed above the tunnel dielectric structure, an insulating layer disposed above the charge storage layer, and a gate electrode disposed above the insulating layer.

Abstract translation: 薄膜晶体管存储单元是可堆叠的，并且采用无结构的NAND配置的带隙工程隧道层，其可以排列成3D阵列。 所述存储单元具有在绝缘层上形成的半导体条中的沟道区，设置在所述沟道区上方的隧道电介质结构，所述隧道电介质结构具有多层结构，所述多层结构包括至少一层具有低于空穴穿透势垒高度的层。 在与沟道区域的界面处，设置在隧道介电结构上方的电荷存储层，设置在电荷存储层上方的绝缘层和设置在绝缘层上方的栅电极。

公开(公告)号：US08363476B2

公开(公告)日：2013-01-29

申请号：US13009464

申请日：2011-01-19

Applicant: Hang-Ting Lue ,  Shih-Hung Chen

Inventor： Hang-Ting Lue ,  Shih-Hung Chen

IPC: G11C16/00

CPC classification number: H01L29/7926 ,  G11C16/0466 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

Abstract: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

Abstract translation: 提供了一种存储器件，其制造方法和操作方法。 存储器件包括衬底，堆叠结构，沟道元件，电介质元件，源元件和位线。 堆叠结构设置在基板上。 每个堆叠结构包括串选择线，字线，接地选择线和绝缘线。 串选择线，字线和接地选择线通过绝缘线彼此分离。 通道元件设置在堆叠结构之间。 电介质元件设置在通道元件和堆叠结构之间。 源元件设置在基板的上表面和通道元件的下表面之间。 位线设置在通道元件的上表面上。

公开(公告)号：US08343840B2

公开(公告)日：2013-01-01

申请号：US12763006

申请日：2010-04-19

Applicant: Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

Inventor： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

IPC: H01L21/336 ,  H01L29/792

CPC classification number: H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

Abstract: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Abstract translation: 带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括 通道由工程隧道电介质。

公开(公告)号：US08324681B2

公开(公告)日：2012-12-04

申请号：US13162386

申请日：2011-06-16

Applicant: Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

Inventor： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/792

Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

Abstract translation: 堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。 位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。 该器件可以配置为NAND操作。

公开(公告)号：US20120220111A1

公开(公告)日：2012-08-30

申请号：US13463264

申请日：2012-05-03

Applicant: Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

Inventor： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

IPC: H01L21/04

CPC classification number: H01L29/665 ,  G11C16/0408 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

Abstract translation: 描述了具有肖特基源和漏极的非易失性存储单元的注入方法。 载流子注入效率由硅化物和硅的界面特性控制。 通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

公开(公告)号：US08252654B2

公开(公告)日：2012-08-28

申请号：US12942312

申请日：2010-11-09

Applicant: Tzu-Hsuan Hsu ,  Hang-Ting Lue

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66833 ,  H01L29/792

Abstract: In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type.

Abstract translation: 在存储单元的制造方法中，设置有基板。 在基板的表面附近形成具有第一导电类型的掺杂区域。 去除衬底的一部分以在衬底中限定多个鳍结构。 在翅片结构之间形成多个隔离结构。 隔离结构的表面低于翅片结构的表面。 栅极结构形成在衬底上并跨越翅片结构。 栅极结构包括跨过鳍结构的栅极和位于鳍结构和栅极之间的电荷存储结构。 源极/漏极区域由栅极结构暴露的鳍状结构中的第二导电类型形成，并且第一导电类型不同于第二导电类型。

公开(公告)号：US20120182807A1

公开(公告)日：2012-07-19

申请号：US13008384

申请日：2011-01-18

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C11/34 ,  H01L21/336 ,  H01L29/792

CPC classification number: H01L27/11556 ,  G11C8/16 ,  G11C16/0416 ,  H01L27/11524

Abstract: A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.

Abstract translation: 3D堆叠的AND型闪速存储器结构包括以三维阵列布置的多个存储单元的水平面，并且每个水平面包括交替布置的多个字线和几个电荷俘获多层，并且相邻的字线与每个 其他每个电荷捕获多层介于其间; 交替布置并垂直于水平面布置的多组位线和源极线; 以及交替布置并且垂直于水平面布置的多组绝缘柱和一组绝缘柱，其中一组通道夹在相邻的位线组和源极线之间。

公开(公告)号：US20120181684A1

公开(公告)日：2012-07-19

申请号：US13009502

申请日：2011-01-19

Applicant: Hang-Ting Lue ,  Yi-Hsuan Hsiao

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC: H01L23/48 ,  H01L21/31

CPC classification number: H01L23/485 ,  H01L24/64 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/792

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.

Abstract translation: 提供半导体结构及其制造方法。 该方法包括以下步骤。 在基板上形成第一含硅导电材料。 在第一含硅导电材料上形成第二含硅导电材料。 第一含硅导电材料和第二含硅导电材料具有不同的掺杂条件。 第一含硅导电材料和第二含硅导电材料被热氧化，以将第一含硅导电材料完全转变成绝缘氧化物结构，第二含硅导电材料变成含硅导电结构， 绝缘氧化物层。

公开(公告)号：US08208279B2

公开(公告)日：2012-06-26

申请号：US12692798

申请日：2010-01-25

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G11C5/02 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，排列成可通过解码电路耦合到读出放大器的位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 导线符合堆叠的表面。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。 存储器元件是可编程的，如抗熔丝或电荷捕获结构。 3D存储器仅使用两层用于多层的关键掩模。

公开(公告)号：US20120051137A1

公开(公告)日：2012-03-01

申请号：US13011717

申请日：2011-01-21

Applicant: Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

Inventor： Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

IPC: G11C16/04 ,  H01L27/08 ,  G11C16/10

CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76838 ,  H01L27/1021 ,  H01L27/11582

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，布置成可以通过解码电路耦合到读出放大器的串。 在字符串的公共源选择端的字符串选择处，二极管连接到位线结构。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。