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    Switchable N-well biasing technique for improved dynamic range and speed performance of analog data bus
    11.
    发明授权
    Switchable N-well biasing technique for improved dynamic range and speed performance of analog data bus 失效
    可切换的N阱偏置技术，用于改善模拟数据总线的动态范围和速度性能

    公开(公告)号：US5939936A

    公开(公告)日：1999-08-17

    申请号：US3264

    申请日：1998-01-06

    Applicant: Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman

    Inventor： Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman

    IPC: H03K17/16 ,  H03K17/693 ,  H03K3/01

    CPC classification number: H03K17/693 ,  H03K17/162 ,  H03K2217/0018

    Abstract: A circuit that includes at least two driver circuits. Each driver circuit receives analog information and drives a value related to the analog information to an analog bus. Each driver circuit also includes a select transistor to pass the value related to the analog information to the analog bus when the driver circuit is selected. The select transistor includes a source and a bulk. Each driver circuit further includes a bulk potential control circuit (BPCC) to couple the bulk to the source when the driver circuit is selected and to couple the bulk to a voltage supply when the driver circuit is not selected.

    Abstract translation: 包括至少两个驱动电路的电路。 每个驱动器电路接收模拟信息并将与模拟信息相关的值驱动到模拟总线。 当选择驱动器电路时，每个驱动电路还包括选择晶体管，以将与模拟信息相关的值传递给模拟总线。 选择晶体管包括源极和体积。 每个驱动器电路还包括当选择驱动器电路时将体耦合到源极的体电势控制电路（BPCC），并且当不选择驱动器电路时将体耦合到电压源。

    Multi-frequency power delivery system
    12.
    发明授权
    Multi-frequency power delivery system 有权
    多频送电系统

    公开(公告)号：US06806569B2

    公开(公告)日：2004-10-19

    申请号：US09964811

    申请日：2001-09-28

    Applicant: James E. Breisch ,  Mark A. Beiley

    Inventor： James E. Breisch ,  Mark A. Beiley

    IPC: H01L2334

    CPC classification number: H01L23/48 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: A mechanism is provided for delivering power to an on-die component (such as a buffer circuit). This may include a package unit having a low frequency delivery path and a high frequency delivery path and a die having the on-die component and a capacitive device each coupled in parallel between a first node and a second node. The die may further include a low frequency reception path and a high frequency reception path. The low frequency reception path may couple to the low frequency delivery path on the package unit and to the first node. The high frequency reception path may couple to the high frequency delivery path on the package unit and to the first node. The high frequency reception path may include a damping resistor.

    Abstract translation: 提供了一种用于将功率传递到片上组件（例如缓冲电路）的机制。 这可以包括具有低频传送路径和高频传送路径的封装单元，以及具有片上部件的管芯和在第一节点和第二节点之间并联耦合的电容器件。 芯片还可以包括低频接收路径和高频接收路径。 低频接收路径可以耦合到封装单元上的低频传送路径和第一节点。 高频接收路径可以耦合到封装单元上的高频传输路径和第一节点。 高频接收路径可以包括阻尼电阻器。

    Slew rate control mechanism
    14.
    发明授权
    Slew rate control mechanism 有权
    压摆率控制机构

    公开(公告)号：US07330993B2

    公开(公告)日：2008-02-12

    申请号：US10675875

    申请日：2003-09-29

    Applicant: Mahesh J. Deshmane ,  Mark A. Beiley ,  Luke A. Johnson

    Inventor： Mahesh J. Deshmane ,  Mark A. Beiley ,  Luke A. Johnson

    IPC: G06F1/04 ,  G06F1/24 ,  G06F11/00

    CPC classification number: G06F13/4072

    Abstract: According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.

    Abstract translation: 根据一个实施例，公开了一种计算机系统。 计算机系统包括总线和耦合到总线的芯片组。 芯片组通过芯片组检测总线上传输的信号的转换速率。 此外，芯片组根据信号的状态调整转换速率。

    Method and apparatus to reduce row reset noise in photodiode
    16.
    发明授权
    Method and apparatus to reduce row reset noise in photodiode 失效
    降低光电二极管行复位噪声的方法和装置

    公开(公告)号：US6133862A

    公开(公告)日：2000-10-17

    申请号：US127310

    申请日：1998-07-31

    Applicant: Jon M. Dhuse ,  Kevin M. Connolly ,  Mark A. Beiley

    Inventor： Jon M. Dhuse ,  Kevin M. Connolly ,  Mark A. Beiley

    IPC: H04N5/363 ,  H04N5/374 ,  H04N5/378 ,  H03M1/06

    CPC classification number: H04N5/363 ,  H04N5/374 ,  H04N5/378

    Abstract: What is disclosed is an apparatus for reducing row reset noise in photodiode based complementary metal oxide (CMOS) sensors. The apparatus uses at least one reference pixel for each row of pixels in a sensor array. Also, a reset noise elimination unit is provided to adjust the values received from the pixels in a particular row by an adjustment value determined from the reset values received from the reference pixels. Additionally, a method of using the apparatus is disclosed. The method has a step of providing a first reset signal to a row of pixels including the reference pixels. The method also reads out a first set of values from this row after integration. The method continues with providing a second reset signal to the row and a second set of values is read from the row. An adjustment value is calculated from the difference of the values which are read out from the reference pixels.

    Abstract translation: 公开的是用于减少基于光电二极管的互补金属氧化物（CMOS）传感器中的行复位噪声的装置。 该装置对传感器阵列中的每行像素使用至少一个参考像素。 此外，提供复位噪声消除单元，用于根据从参考像素接收的复位值确定的调整值来调整从特定行中的像素接收的值。 另外，公开了一种使用该装置的方法。 该方法具有向包括参考像素的像素行提供第一复位信号的步骤。 该方法还从集成后的第一行中读出第一组值。 该方法继续向该行提供第二复位信号，并且从该行读取第二组值。 根据从参考像素读出的值的差来计算调整值。

    Method and apparatus to produce a random bit sequence
    18.
    发明授权
    Method and apparatus to produce a random bit sequence 有权
    产生随机比特序列的方法和装置

    公开(公告)号：US06362695B1

    公开(公告)日：2002-03-26

    申请号：US09468478

    申请日：1999-12-21

    Applicant: Mark A. Beiley ,  James E. Breisch

    Inventor： Mark A. Beiley ,  James E. Breisch

    IPC: H03B2900

    CPC classification number: H03K3/84

    Abstract: A circuit includes a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors.

    Abstract translation: 电路包括具有晶体管以产生由晶体管的器件沟道电阻产生的随机变化的第一信号的第一振荡器。

    Imaging system having a sensor array reset noise reduction mechanism
    20.
    发明授权
    Imaging system having a sensor array reset noise reduction mechanism 失效
    具有传感器阵列复位噪声降低机构的成像系统

    公开(公告)号：US06438276B1

    公开(公告)日：2002-08-20

    申请号：US09659159

    申请日：2000-09-11

    Applicant: Jon M. Dhuse ,  Kevin M. Connolly ,  Mark A. Beiley

    Inventor： Jon M. Dhuse ,  Kevin M. Connolly ,  Mark A. Beiley

    IPC: G06K920

    CPC classification number: H04N5/363 ,  H04N5/374 ,  H04N5/378

    Abstract: What is disclosed is an apparatus for reducing row reset noise in photodiode based complementary metal oxide (CMOS) sensors. The apparatus uses at least one reference pixel for each row of pixels in a sensor array. Also, a reset noise elimination unit is provided to adjust the values received from the pixels in a particular row by an adjustment value determined from the reset values received from the reference pixels. Additionally, a method of using the apparatus is disclosed. The method has a step of providing a first reset signal to a row of pixels including the reference pixels. The method also reads out a first set of values from this row after integration. The method continues with providing a second reset signal to the row and a second set of values is read from the row. An adjustment value is calculated from the difference of the values which are read out from the reference pixels.

    Abstract translation: 公开的是用于减少基于光电二极管的互补金属氧化物（CMOS）传感器中的行复位噪声的装置。 该装置对传感器阵列中的每行像素使用至少一个参考像素。 此外，提供复位噪声消除单元，用于根据从参考像素接收的复位值确定的调整值来调整从特定行中的像素接收的值。 另外，公开了一种使用该装置的方法。 该方法具有向包括参考像素的像素行提供第一复位信号的步骤。 该方法还从集成后的第一行中读出第一组值。 该方法继续向该行提供第二复位信号，并且从该行读取第二组值。 根据从参考像素读出的值的差来计算调整值。

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