公开(公告)号：US20060044907A1

公开(公告)日：2006-03-02

申请号：US10931786

申请日：2004-09-01

Applicant: Leonard Forbes ,  David Cuthbert

Inventor： Leonard Forbes ,  David Cuthbert

IPC: G11C7/02

CPC classification number: G11C27/026 ,  G11C7/062 ,  G11C11/4091

Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.

Abstract translation: 存储读出放大器包括一个采样和保持电路，后跟一个差分放大器。 当在位线中存在表示数据位的信号时，采样和保持电路在存储器电路的位线上对基准电压进行采样，当读出放大器被复位时，信号电压位于同一位线上。 差分放大器放大信号电压和参考电压之间的差值。

公开(公告)号：US20060044066A1

公开(公告)日：2006-03-02

申请号：US10931796

申请日：2004-09-01

Applicant: Leonard Forbes ,  David Cuthbert

Inventor： Leonard Forbes ,  David Cuthbert

IPC: H03F1/14

CPC classification number: H03F3/45183 ,  H03F1/08 ,  H03F1/14 ,  H03F3/45273 ,  H03F2203/45264 ,  H03F2203/45332

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

公开(公告)号：US06675313B2

公开(公告)日：2004-01-06

申请号：US10329494

申请日：2002-12-27

Applicant: David Cuthbert

Inventor： David Cuthbert

IPC: G06F104

CPC classification number: H05K1/0248 ,  G06F1/10 ,  H05K1/0293 ,  H05K3/027 ,  H05K2201/09263 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/0979 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1115 ,  H05K2203/1338 ,  H05K2203/171 ,  H05K2203/175

Abstract: An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.

Abstract translation: 描述了一种用于减少包括互连第一节点和第二节点的多个导电迹线的印刷电路板上的定时偏移的装置和方法。 至少一个部分从至少一个印刷电路板迹线移除，从而切断迹线并防止从第一节点传递到第二节点的信号不跟随切断的迹线。 以这种方式，可以调整信号路径长度以减少电路中的定时偏差。 通过使用激光，CVD，路由器，等离子体或者通过使足够的电流通过弱化区域从迹线中去除部分。

公开(公告)号：US20070054550A1

公开(公告)日：2007-03-08

申请号：US11278541

申请日：2006-04-03

Applicant: David Cuthbert ,  Larry Rogel ,  Matthew Page ,  James Page

Inventor： David Cuthbert ,  Larry Rogel ,  Matthew Page ,  James Page

IPC: H01R13/648

CPC classification number: H01R29/00 ,  H01R27/02 ,  H01R2201/04 ,  H01R2201/06

Abstract: An apparatus which provides the ability to charge or power multiple devices from multiple different power sources, and to communicate electronic data to and from one of the devices. The apparatus utilizes simple construction, requiring no active electronics, thereby reducing the cost of production and the reliability of the device. The apparatus employs a single USB connection cable with connectors on both ends and a second power-only cable and connector which is connected to the power wires of the USB cable and thereby is able to power a second portable device from a single USB port. USB master provide sufficient power for two average portable devices without additional circuitry. Moreover, restricting the data path to only one device also eliminates the need for USB hub circuitry. Finally, greater end user flexibility is provided by using a USB male connector as the source of the data and power connection, a USB female connector for the output of the data and power connection, and a standard barrel-type power connector for the power-only output connection. Having two different output connectors ensures that the user will not confuse the two connectors.

Abstract translation: 一种提供从多个不同电源对多个设备进行充电或供电的能力以及将电子数据传送到设备之一或从设备之一传送电子数据的设备。 该设备采用简单的结构，不需要有源电子元件，从而降低了生产成本和设备的可靠性。 该装置采用单个USB连接电缆，其两端具有连接器，以及第二电源电缆和连接器，其连接到USB电缆的电源线，从而能够从单个USB端口为第二便携式设备供电。 USB主机为两个平均的便携式设备提供足够的电力，无需额外的电路。 而且，将数据路径限制在一个设备上也不需要USB集线器电路。 最后，通过使用USB公连接器作为数据和电源连接的来源，提供用于输出数据和电源连接的USB母连接器以及用于电源连接的标准机筒式电源连接器来提供更大的终端用户灵活性， 只输出连接。 具有两个不同的输出连接器可确保用户不会混淆两个连接器。

公开(公告)号：US20050206400A1

公开(公告)日：2005-09-22

申请号：US11142226

申请日：2005-06-01

Applicant: William Casey ,  David Cuthbert ,  Olivia McGrew

Inventor： William Casey ,  David Cuthbert ,  Olivia McGrew

IPC: G01R31/28 ,  H05K1/02 ,  H05K1/11 ,  G01R31/02

CPC classification number: H05K1/0268 ,  G01R31/2889 ,  H05K1/112 ,  H05K2201/09781

Abstract: An integrated circuit characterization printed circuit board and method are provided for improving the uniformity of impedance introduced by a test fixture across all of the pins of an integrated circuit device. The printed circuit board includes an array of substantially similar test contacts numbering greater than the pins of the integrated circuit device. The array of test contacts includes an active portion configured for electrically coupling with the corresponding pins on the integrated circuit device and an inactive portion adjacent to the active portion and electrically coupled to a reference signal on the printed circuit board.

Abstract translation: 提供了一种集成电路表征印刷电路板和方法，用于改善由集成电路器件的所有引脚上的测试夹具引入的阻抗的均匀性。 印刷电路板包括大致类似的测试触头的阵列，编号大于集成电路器件的引脚。 测试触点阵列包括被配置用于与集成电路器件上的相应引脚电耦合的有源部分和与有源部分相邻的非活动部分，并电耦合到印刷电路板上的参考信号。

公开(公告)号：US20060043987A1

公开(公告)日：2006-03-02

申请号：US11269047

申请日：2005-11-07

Applicant: Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

Inventor： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC: G01R31/02

CPC classification number: G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

Abstract translation: 提供了用于使用网络分析仪与同轴测试探针一起测量任何类型或配置的集成电路封装中的互耦合的可能性的方法。 简单，低成本的测试夹具和测试方法可用于测量集成电路封装的一个或多个I / O引线的寄生电容和电感，所测量的寄生电容和电感提供了集成电路的易感性指示 电路封装以在封装的电引线之间或电引线和集成电路封装的其它部件之间相互耦合。

公开(公告)号：US20050024039A1

公开(公告)日：2005-02-03

申请号：US10927578

申请日：2004-08-25

Applicant: William Casey ,  David Cuthbert ,  Olivia McGrew

Inventor： William Casey ,  David Cuthbert ,  Olivia McGrew

IPC: G01R31/28 ,  H05K1/02 ,  H05K1/11 ,  G01R1/00

CPC classification number: H05K1/0268 ,  G01R31/2889 ,  H05K1/112 ,  H05K2201/09781

Abstract: An integrated circuit characterization printed circuit board and method are provided for improving the uniformity of impedance introduced by a test fixture across all of the pins of an integrated circuit device. The printed circuit board includes an array of substantially similar test contacts numbering greater than the pins of the integrated circuit device. The array of test contacts includes an active portion configured for electrically coupling with the corresponding pins on the integrated circuit device and an inactive portion adjacent to the active portion and electrically coupled to a reference signal on the printed circuit board.

Abstract translation: 提供了一种集成电路表征印刷电路板和方法，用于改善由集成电路器件的所有引脚上的测试夹具引入的阻抗的均匀性。 印刷电路板包括大致类似的测试触头的阵列，编号大于集成电路器件的引脚。 测试触点阵列包括被配置用于与集成电路器件上的相应引脚电耦合的有源部分和与有源部分相邻的非活动部分，并电耦合到印刷电路板上的参考信号。

公开(公告)号：US20050184917A1

公开(公告)日：2005-08-25

申请号：US10781806

申请日：2004-02-20

Applicant: David Cuthbert

Inventor： David Cuthbert

IPC: H01Q9/30 ,  H01Q9/38 ,  H01Q11/12 ,  H01Q21/00

CPC classification number: H01Q9/38 ,  H01Q9/30

Abstract: A low profile antenna having relatively high radiation resistance, wide bandwidth and which utilizes a single conductor and RF source is disclosed. In accordance with an exemplary embodiment, the upper horizontal portion and the lower horizontal portion of the double inverted-L antenna are respectively brought down and up (without being physically connected) at a distance of approximately 180 degrees (½ λ) from the RF source so as to form two additional vertical portions of the antenna. This is followed by two approximately 90-degree (¼ λ) horizontal conductors portion. The resulting radiation resistance of the low profile antenna is approximately three-times that of a double inverted-L antenna.

Abstract translation: 公开了一种具有较高辐射电阻，宽带宽并且利用单导体和RF源的低剖面天线。 根据示例性实施例，双倒L型天线的上水平部分和下水平部分分别在与RF源大约180度（½λ）的距离处被下降和向上（不被物理连接）） 以形成天线的另外两个垂直部分。 其后是两个约90度（¼λ）的水平导体部分。 低频天线所产生的辐射电阻大约是双倒L型天线的辐射电阻的三倍。

公开(公告)号：US20050161801A1

公开(公告)日：2005-07-28

申请号：US11083591

申请日：2005-03-18

Applicant: Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

Inventor： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC: G01R1/04 ,  G01R27/26 ,  H01L23/52

CPC classification number: G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

公开(公告)号：US20050161256A1

公开(公告)日：2005-07-28

申请号：US11083506

申请日：2005-03-18

Applicant: Mark Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

Inventor： Mark Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC: G01R1/04 ,  G01R27/26 ,  H05K1/11 ,  H01R12/04

CPC classification number: G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

Abstract translation: 提供了装置和方法，用于使用网络分析仪结合同轴测试探针来测量任何类型或配置的集成电路封装中的互耦合的可能性。 简单，低成本的测试夹具和测试方法可用于测量集成电路封装的一个或多个I / O引线的寄生电容和电感，所测量的寄生电容和电感提供了集成电路的易感性指示 电路封装以在封装的电引线之间或电引线和集成电路封装的其它部件之间相互耦合。