公开(公告)号：US06934182B2

公开(公告)日：2005-08-23

申请号：US10678508

申请日：2003-10-03

申请人： Yuen H. Chan ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Robert Chi-Foon Wong

发明人： Yuen H. Chan ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Robert Chi-Foon Wong

IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/412

摘要： Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

摘要翻译： 提供了设计具有更大稳定性和/或更小单元尺寸的6T SRAM单元的方法。 6T SRAM单元具有一对存取晶体管（NFET），一对上拉晶体管（PFET）和一对下拉晶体管（NFET），其中存取晶体管具有比下拉电阻高的阈值电压 晶体管，这使得SRAM单元能够在单元访问期间有效地保持逻辑“0”，从而增加了单元的稳定性，特别是对于“半选择”期间的单元。 此外，可以减小下拉晶体管的沟道宽度，从而降低高性能六晶体管SRAM单元的尺寸，而不影响单元在访问期间的稳定性。 并且，通过减小单元尺寸，芯片的整体设计布局也可能降低。

公开(公告)号：US06714476B2

公开(公告)日：2004-03-30

申请号：US09783918

申请日：2001-02-15

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

IPC分类号： G11C800

CPC分类号： G11C8/14 ,  G11C8/10 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4087

摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Wordline decoding circuitry is included for interchanging the DRAM array between single-cell and twin-cell array operation. The wordline decoding circuitry includes a pre-decoder circuit for receiving a control signal and outputting logic outputs to wordline activation circuitry. The wordline activation circuitry then activates at least one wordline traversing the array for interchanging memory cells within the DRAM array between single-cell array operation and twin-cell array operation. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.

摘要翻译： 提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。 优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。 包括字线解码电路，用于在单电池和双电池阵列操作之间交换DRAM阵列。 字线解码电路包括用于接收控制信号并将逻辑输出输出到字线激活电路的预解码器电路。 字线激活电路然后激活穿过阵列的至少一个字线，用于在单电池阵列操作和双电池阵列操作之间互换DRAM阵列内的存储器单元。 还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

公开(公告)号：US06549450B1

公开(公告)日：2003-04-15

申请号：US09708142

申请日：2000-11-08

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi ,  Mary J. Saccamango

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi ,  Mary J. Saccamango

IPC分类号： G11C1100

CPC分类号： G11C11/419

摘要： The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized. In the SOI SRAM architecture system of the present invention, before the SOI SRAM array is first accessed following the idle or sleep mode, the bitlines are quickly brought up to Vdd. Accordingly, there will not be sufficient time for the SOI body regions of the transfer devices to be charged up. Following access of the array, if the array becomes idle for a period of time, the bitlines are discharged to a lower voltage level again. To realize this, the SOI SRAM architecture system of the present invention includes circuitry for receiving at least one signal indicative of the operating mode of the array and for charging and discharging the array bitlines accordingly.

摘要翻译： 本发明提供一种SOI SRAM架构系统，其在阵列空闲或睡眠模式期间将所有位线保持在较低电压电平，例如接地或Vdd的一部分。 优选地，位线被保持在大约等于Vdd-Vth的电压电平，其中Vth表示SRAM单元的传送器件的阈值电压。 这防止了阵列的每个电池的转移装置的主体区域完全充电，因此系统避免了由部分耗尽的SOI衬底上制造的器件引起的寄生双极泄漏电流效应。 而且，在空闲或睡眠模式期间，如果所有位线都保持在Vdd-Vth电压电平左右，则SRAM架构系统的功耗将会降低。 这是因为通过所有SRAM单元的传输门之一的泄漏路径被极大地最小化。 在本发明的SOI SRAM架构系统中，在空闲或休眠模式之前首先访问SOI SRAM阵列之前，位线被快速地提升到Vdd。 因此，传送装置的SOI体区域不会充足的时间。 在阵列访问之后，如果阵列空闲一段时间，则位线再次放电到较低的电压电平。 为了实现这一点，本发明的SOI SRAM架构系统包括用于接收指示阵列的操作模式的至少一个信号并且相应地对阵列位线进行充电和放电的电路。

公开(公告)号：US06452855B1

公开(公告)日：2002-09-17

申请号：US09755868

申请日：2001-01-05

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  John A. Fifield ,  Wayne F. Ellis

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  John A. Fifield ,  Wayne F. Ellis

IPC分类号： H01L27118

CPC分类号： G11C7/1045 ,  G11C7/1006 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097

摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.

摘要翻译： 提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。 优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。 包括开关电路用于单电池和双电池阵列操作之间的互换，反之亦然。 还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

公开(公告)号：US06445626B1

公开(公告)日：2002-09-03

申请号：US09821443

申请日：2001-03-29

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Gregory J. Fredeman

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Gregory J. Fredeman

IPC分类号： G11C700

CPC分类号： G11C29/848 ,  G11C29/846 ,  G11C2207/104

摘要： A column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width is disclosed which provides column redundancy to defective datalines of the eDRAM. Internally generated column addresses of defective columns of each micro cell block are stored in a memory device during eDRAM array testing. Two redundancy reroute mechanisms are disclosed. The first redundancy reroute mechanism selects at least one defective dataline of the eDRAM and directly replaces the defective dataline(s) with at least one redundancy dataline. The second redundancy reroute mechanism discards the defective dataline column and replaces it with an adjacent dataline column. The dataline columns following the defective dataline column are then replaced with the next adjacent dataline columns including a redundancy dataline column.

摘要翻译： 公开了一种具有宽数据带宽和宽内部总线宽度的嵌入式DRAM（eDRAM）的列冗余架构系统，其为eDRAM的缺陷数据库提供列冗余。 在eDRAM阵列测试期间，每个微单元块的内部生成的列地址存储在存储器件中。 公开了两种冗余重路由机制。 第一个冗余重路由机制选择eDRAM的至少一个有缺陷的数据库，并用至少一个冗余数据线直接替换有缺陷的数据库。 第二个冗余重路由机制丢弃有缺陷的数据列，并用相邻的数据列替换它。 随后，数据线列中的数据栏将被替换为包含冗余数据列的下一个相邻的数据列。

公开(公告)号：US06337595B1

公开(公告)日：2002-01-08

申请号：US09627599

申请日：2000-07-28

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton ,  Wayne F. Ellis ,  Jeffrey H. Dreibelbis

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton ,  Wayne F. Ellis ,  Jeffrey H. Dreibelbis

IPC分类号： G05F302

CPC分类号： G05F3/265

摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

公开(公告)号：US06323554B1

公开(公告)日：2001-11-27

申请号：US09113916

申请日：1998-07-10

申请人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

发明人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959 ,  H01L2924/00

摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH4 to WF6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

摘要翻译： 用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损性质不会划伤，腐蚀或涂抹。 使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生导电线和通孔。 在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。 准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。 理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的 散射沉积占主导地位的真空压力（例如高于1mTorr）。 对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

公开(公告)号：US6147402A

公开(公告)日：2000-11-14

申请号：US113918

申请日：1998-07-10

申请人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

发明人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC分类号： H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/440 ,  H01L29/460

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959

摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

摘要翻译： 用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损特性不会划伤，腐蚀或涂抹。 使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。 在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。 准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。 理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的 散射沉积占主导地位的真空压力（例如高于1mTorr）。 对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

公开(公告)号：US5976975A

公开(公告)日：1999-11-02

申请号：US113917

申请日：1998-07-10

申请人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

发明人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC分类号： H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959

摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the-hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below lmtorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

摘要翻译： 用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损特性不会划伤，腐蚀或涂抹。 使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。 在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。 准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。 理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mtorr），并且在较高真空下沉积第二层 散射沉积占主导地位的压力（例如高于1mTorr）。 对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

公开(公告)号：US5403779A

公开(公告)日：1995-04-04

申请号：US928335

申请日：1992-08-12

申请人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

发明人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC分类号： H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959

摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

摘要翻译： 用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损性质不会划伤，腐蚀或涂抹。 使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。 在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。 准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。 理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的 散射沉积占主导地位的真空压力（例如高于1mTorr）。 对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。