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    Read Performance of Memory Devices
    11.
    发明申请
    Read Performance of Memory Devices 有权

    公开(公告)号：US20210342094A1

    公开(公告)日：2021-11-04

    申请号：US16863202

    申请日：2020-04-30

    Applicant: Macronix International Co., Ltd.

    Inventor： Ting-Yu Liu ,  Yi-Chun Liu

    IPC: G06F3/06 ,  G06F12/10 ,  G06F12/123

    Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

    Programming A Memory Device
    13.
    发明申请
    Programming A Memory Device 审中-公开

    公开(公告)号：US20200273529A1

    公开(公告)日：2020-08-27

    申请号：US16281258

    申请日：2019-02-21

    Applicant: Macronix International Co., Ltd.

    Inventor： Yi-Chun Liu

    IPC: G11C16/34 ,  G06F11/10 ,  G06F3/06 ,  G11C29/00 ,  G11C29/42 ,  G11C11/56 ,  G11C16/16 ,  G11C16/08 ,  G11C16/24

    Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

    MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME
    16.
    发明申请
    MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20180165219A1

    公开(公告)日：2018-06-14

    申请号：US15375545

    申请日：2016-12-12

    Applicant: Macronix International Co., Ltd.

    Inventor： Tzu-Yi Yang ,  Ting-Yu Liu ,  Yi-Chun Liu

    IPC: G06F12/121 ,  G06F3/06

    CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/068 ,  G06F12/0638 ,  G06F2212/1016

    Abstract: A request is received to load a particular overlay segment from a secondary storage memory to a main memory for execution by a processor, wherein the particular overlay segment is absent from the main memory. A determination is made whether the main memory can receive the particular overlay segment. In response to determining that the main memory cannot receive the particular overlay segment, eviction strategy information about one or more existing overlay segments that are present in the main memory is obtained. Based on the eviction strategy information, at least one of the one or more existing overlay segments is selected for eviction from the main memory. The particular overlay segment is retrieved from the secondary storage memory. The at least one of the one or more existing overlay segments in the main memory that is selected for eviction is replaced with the particular overlay segment.

    READ PERFORMANCE OF MEMORY DEVICES
    17.
    发明公开
    READ PERFORMANCE OF MEMORY DEVICES 审中-公开

    公开(公告)号：US20230214158A1

    公开(公告)日：2023-07-06

    申请号：US18175726

    申请日：2023-02-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Ting-Yu Liu ,  Yi-Chun Liu

    IPC: G06F3/06 ,  G06F12/123 ,  G06F12/10

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F12/124 ,  G06F12/10 ,  G06F3/0674

    Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

    Methods and systems for managing physical information of memory units in a memory device
    19.
    发明授权
    Methods and systems for managing physical information of memory units in a memory device 有权

    公开(公告)号：US10990528B2

    公开(公告)日：2021-04-27

    申请号：US16418428

    申请日：2019-05-21

    Applicant: Macronix International Co., Ltd.

    Inventor： Yi-Chun Liu

    IPC: G06F12/0868 ,  G06F12/0815 ,  G06F12/0895 ,  G06F12/0817 ,  G06F12/02 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/0804

    Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.

    Memory system, memory controller, and memory control method
    20.
    发明授权
    Memory system, memory controller, and memory control method 有权

    公开(公告)号：US10916310B2

    公开(公告)日：2021-02-09

    申请号：US16408526

    申请日：2019-05-10

    Applicant: Macronix International Co., Ltd.

    Inventor： Yi-Chun Liu ,  Yiching Liu

    IPC: G11C16/04 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

    Abstract: Methods, systems and apparatus including computer-readable mediums for partially erasing blocks in a memory system to increase reliability are provided. In one aspect, a memory system includes a memory having a plurality of blocks and a memory controller coupled to the memory. The memory controller is configured to: execute a first erase operation on a particular block in the memory, the particular block including multiple sub-blocks each having respective memory cells, one or more memory cells in the particular block being in one or more programmed states before the first erase operation, then execute a second erase operation on a first sub-block of the particular block such that first respective memory cells of the first sub-block are in an erased state after the second erase operation. The memory controller can be configured to not execute the second erase operation on the one or more other sub-blocks of the particular block.

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