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    Method for manufacturing memory device
    11.
    发明授权
    Method for manufacturing memory device 有权

    公开(公告)号：US12114514B2

    公开(公告)日：2024-10-08

    申请号：US18519230

    申请日：2023-11-27

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Feng-Min Lee ,  Erh-Kun Lai ,  Dai-Ying Lee ,  Yu-Hsuan Lin ,  Po-Hao Tseng ,  Ming-Hsiu Lee

    IPC: H10N50/01 ,  H10B61/00 ,  H10B63/00 ,  H10N70/00

    CPC classification number: H10B63/845 ,  H10B61/22 ,  H10B63/34 ,  H10N50/01 ,  H10N70/066

    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

    Analog content-address memory having approximation matching and operation method thereof
    12.
    发明授权
    Analog content-address memory having approximation matching and operation method thereof 有权

    公开(公告)号：US11875849B2

    公开(公告)日：2024-01-16

    申请号：US17711073

    申请日：2022-04-01

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee

    IPC: G11C15/04

    CPC classification number: G11C15/046

    Abstract: An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.

    In-Memory Computing Devices for Neural Networks
    14.
    发明申请
    In-Memory Computing Devices for Neural Networks 审中-公开

    公开(公告)号：US20200026991A1

    公开(公告)日：2020-01-23

    申请号：US16224602

    申请日：2018-12-18

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Hsuan Lin ,  Chao-Hung Wang ,  Ming-Hsiu Lee

    IPC: G06N3/063 ,  G11C11/54 ,  G11C27/00 ,  G11C7/10

    Abstract: An in-memory computing device includes a plurality of synaptic layers including a first type of synaptic layer and a second type of synaptic layer. The first type of synaptic layer comprises memory cells of a first type of memory cell and the second type of synaptic layer comprises memory cells of a second type, the first type of memory cell being different than the second type of memory cell. The first and second types of memory cells can be different types of memories, have different structures, different memory materials, and/or different read/write algorithms, any one of which can result in variations in the stability or accuracy of the data stored in the memory cells.

    Semiconductor memory device and operation method thereof
    15.
    发明授权
    Semiconductor memory device and operation method thereof 有权

    公开(公告)号：US09947398B1

    公开(公告)日：2018-04-17

    申请号：US15482978

    申请日：2017-04-10

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan Lin ,  Kai-Chieh Hsu ,  Yu-Yu Lin ,  Feng-Min Lee

    IPC: G11C11/00 ,  G11C13/00 ,  G06F1/32

    CPC classification number: G11C13/0038 ,  G11C13/004 ,  G11C2013/0054

    Abstract: A semiconductor memory device includes: a memory array including a plurality of memory cells, the memory cells being in any of a high resistance state (HRS) and a low resistance state (LRS); a reference array including a plurality of reference cells, the memory cells and the reference cells having the same impedance-temperature relationship, the reference cells being in a middle resistance state between HRS and LRS; an average circuit configured for averaging respective reference currents from the reference cells of the reference array into an average reference current; and a comparator configured for comparing a plurality of respective memory currents from the memory cells of the memory array with the average reference current to obtain a plurality of output data of the memory cells of the memory array and to determine respective impedance states of the memory cells of the memory array.

    In-dynamic memory search device and operation method thereof
    17.
    发明授权
    In-dynamic memory search device and operation method thereof 有权

    公开(公告)号：US12159671B2

    公开(公告)日：2024-12-03

    申请号：US18164657

    申请日：2023-02-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Yu-Hsuan Lin

    IPC: G11C15/04

    Abstract: An in-dynamic memory search device and an operation method thereof are provided. The in-dynamic memory search device includes at least one word line, at least two bit lines, at least one match line, at least one unit cell, at least two search lines, at least one pre-charge unit and at least one sense unit. The unit cell includes two storage elements and two search transistors. Each of the storage elements includes a write transistor and a read transistor. The write transistor is connected to the word line and one of the bit lines. The read transistor is connected to the write transistor and the match line. The search transistors are respectively connected to the read transistors. The search lines are respectively connected to the search transistors. The pre-charge unit is connected to the match line. The sense unit is connected to the match line.

    ARTIFICIAL NEURAL NETWORK OPERATION CIRCUIT AND IN-MEMORY COMPUTATION DEVICE THEREOF
    18.
    发明公开
    ARTIFICIAL NEURAL NETWORK OPERATION CIRCUIT AND IN-MEMORY COMPUTATION DEVICE THEREOF 审中-公开

    公开(公告)号：US20240282382A1

    公开(公告)日：2024-08-22

    申请号：US18172306

    申请日：2023-02-22

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Hsuan Lin ,  Yu-Yu Lin ,  Hsiang-Lan Lung

    IPC: G11C16/12 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/24

    Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

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