公开(公告)号：US09270272B2

公开(公告)日：2016-02-23

申请号：US14467419

申请日：2014-08-25

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen

IPC: G06F1/12 ,  G06F1/00 ,  G06F1/04 ,  G06F3/02 ,  G06F3/16 ,  H03B5/32 ,  H03K19/0175 ,  G06F1/08 ,  G05F3/02 ,  H03L5/00 ,  G06F1/10

CPC classification number: H03K19/018528 ,  G05F3/02 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  H03K19/0175 ,  H03L5/00

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

公开(公告)号：US08947961B2

公开(公告)日：2015-02-03

申请号：US13950942

申请日：2013-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Lung Yi Kuo ,  Hsin Yi Ho ,  Chun Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen ,  Shih-Chou Juan

IPC: G11C16/04 ,  G11C16/06 ,  G11C29/00 ,  G11C16/10 ,  G11C29/04

CPC classification number: G11C16/10 ,  G11C29/808 ,  G11C29/82 ,  G11C2029/4402

Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.

Abstract translation: 一种用于编程包括多个块的非易失性存储器的方法，每个块包括多个部分，每个部分包括至少一个页面，并且每个页面包括多个存储器单元。 该方法包括根据损坏部分表检查多个部分的当前部分，以确定当前部分是否损坏。 损坏的部分表记录有关内存中的部分是好还是损坏的信息。 该方法还包括如果当前部分没有损坏，则使用当前部分进行编程。

公开(公告)号：US20140281150A1

公开(公告)日：2014-09-18

申请号：US13926633

申请日：2013-06-25

Applicant: Macronix International Co., Ltd.

Inventor： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Han-Sung Chen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.

Abstract translation: 一种用于维护数据集的方法包括将数据集的基本副本存储在具有第一写入速度的第一非易失性存储器中，将具有第一非易失性存储器的第一变化数据集中的数据集的改变存储在具有第 第二写入速度，并通过读取基本副本和更改来生成数据集的当前副本。 如果达到第一改变数据集中的阈值数目，则将第一变化数据集的部分或全部移动到第一非易失性存储器中的第二变化数据集中，其中生成步骤包括读取第二变化 数据集。 如果达到第二改变数据集中的阈值数目，则通过读取基本副本和第一和第二非易失性存储器中的改变来生成当前副本。

公开(公告)号：US11488657B1

公开(公告)日：2022-11-01

申请号：US17234236

申请日：2021-04-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Jen-Hung Huang ,  Han-Sung Chen

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04

Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks while disabling current flow. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks. The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.

公开(公告)号：US09977627B1

公开(公告)日：2018-05-22

申请号：US15346790

申请日：2016-11-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Han-Sung Chen ,  Chung-Kuang Chen

IPC: G11C7/00 ,  G06F3/06 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/3431 ,  G11C16/3495

Abstract: A memory device includes a memory unit including a plurality of memory cells, and a controller including a storage unit that stores a plurality of operation selections each corresponding to a property of at least one selected memory cell among the plurality of memory cells.

公开(公告)号：US20180123592A1

公开(公告)日：2018-05-03

申请号：US15858783

申请日：2017-12-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： CHUNG-KUANG CHEN ,  CHUN-HSIUNG HUNG ,  Han-Sung Chen

IPC: H03K19/0185 ,  G06F1/08 ,  H03L5/00 ,  G05F3/02 ,  G06F1/04

CPC classification number: H03K19/018528 ,  G05F3/02 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  H03K19/0175 ,  H03L5/00

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

公开(公告)号：US09887009B2

公开(公告)日：2018-02-06

申请号：US14513899

申请日：2014-10-14

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chung-Hsiung Hung

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C7/10 ,  G11C11/56 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C7/1084 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5621

Abstract: One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.

公开(公告)号：US09589646B2

公开(公告)日：2017-03-07

申请号：US14554293

申请日：2014-11-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C16/04 ,  G11C16/10 ,  G06F3/06 ,  G11C7/02

CPC classification number: G11C16/10 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G11C7/02 ,  G11C16/0483

Abstract: A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first page buffer, and input data of at least one neighboring page buffer. The first page buffer is also configured to apply a bias corresponding to the input data of the first page buffer, and the input data of the at least one neighboring page buffer to a bit line.

Abstract translation: 页面缓冲电路包括多个页缓冲器，包括第一页缓冲器。 第一页缓冲器被配置为加载第一页缓冲器的输入数据，并输入至少一个相邻页缓冲器的数据。 第一页缓冲器还被配置为将与第一页缓冲器的输入数据相对应的偏置以及至少一个相邻页缓冲器的输入数据施加到位线。

公开(公告)号：US20160203878A1

公开(公告)日：2016-07-14

申请号：US14595252

申请日：2015-01-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C29/50 ,  G11C29/00 ,  G11C7/10

CPC classification number: G11C29/50016 ,  G11C7/02 ,  G11C7/1036 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427 ,  G11C16/3459 ,  G11C19/00 ,  G11C29/86 ,  G11C2211/5621

Abstract: An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.

Abstract translation: 存储器件的操作方法包括以下步骤：第一页缓冲器接收要被编程到存储器单元的第一存储器单元中的第一输入数据; 第二页缓冲器接收要编程到存储器单元的第二存储单元中的第二输入数据; 并且第一页缓冲器根据第一和第二输入数据确定是否移位用于第一输入数据的程序验证（PV）电压。

公开(公告)号：US09152557B2

公开(公告)日：2015-10-06

申请号：US14265400

申请日：2014-04-30

Applicant: Macronix International Co., Ltd.

Inventor： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen

IPC: G06F3/06 ,  G06F12/02 ,  G11C16/10 ,  G11C11/56 ,  G06F11/00

CPC classification number: G06F12/0246 ,  G06F11/00 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C16/10 ,  G11C16/105 ,  G11C2211/5648

Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.

Abstract translation: 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。