-
公开(公告)号：US20230185280A1
公开(公告)日：2023-06-15
申请号：US17993853
申请日：2022-11-23
Applicant: MEDIATEK INC.
Inventor： Chih-Fu Tsai , Yu-Chia Chang , Bo-Jiun Yang , Yen-Hwei Hsieh , Shun-Yao Yang , Jia-Wei Fang , Ta-Chang Liao , Tai-Yu Chen
IPC: G05B19/4155
CPC classification number: G05B19/4155 , G05B2219/50333
Abstract: An integrated circuit (IC) configurable to perform adaptive thermal ceiling control in a per-functional-block manner, an associated main circuit, an associated electronic device and an associated thermal control method are provided. The IC may include a plurality of hardware circuits arranged to perform operations of a first functional block, and at least one thermal control circuit. At least one temperature sensor is coupled with the first functional block to detect temperature and to generate at least one temperature sensing result of the first functional block. The thermal control circuit performs thermal control on the first functional block to prevent the first functional block from overheating and inducing abnormal function operations, by monitoring the temperature sensing result and by trying to prevent the temperature sensing result from exceeding first temperature upper-limit, wherein the first temperature upper-limit is configurable with respect to per-functional-block thermal operation capability of the first functional block.
-
公开(公告)号：US09660017B2
公开(公告)日：2017-05-23
申请号：US14925995
申请日：2015-10-29
Applicant: MEDIATEK INC.
Inventor： Chao-Yang Yeh , Chee-Kong Ung , Tzu-Hung Lin , Jia-Wei Fang
CPC classification number: H01L28/40 , H01L23/3157 , H01L23/49816 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/16 , H01L28/10 , H01L28/20 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/16265 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15159 , H01L2924/15311 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/014
Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.
-
13.发明授权Method and apparatus for flip chip packaging co-design and co-designed flip chip package 有权用于倒装芯片封装的方法和装置共同设计和共同设计的倒装芯片封装公开(公告)号：US09552452B2
公开(公告)日：2017-01-24
申请号：US15088109
申请日：2016-03-31
Applicant: MEDIATEK INC.
Inventor： Jia-Wei Fang , Shen-Yu Huang
CPC classification number: G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/40 , G06F2217/78 , H01L24/06 , H01L24/14 , H01L2224/0612 , H01L2224/1412 , H01L2224/73204 , H01L2224/81 , H01L2224/97 , H01L2225/06517 , H01L2924/15311 , H01L2924/00014
Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.
Abstract translation: 本发明提供了一种倒装芯片封装协同设计方法。 该方法包括以下步骤：提供芯片的I / O焊盘信息和PCB的连接信息; 根据芯片的I / O焊盘信息和PCB的连接信息执行第一I / O焊盘放置; 利用RDL路由分析装置对芯片的第一I / O焊盘放置执行凸块焊盘间距分析以产生凸块焊盘间距分析结果; 根据凸点焊盘间距分析结果对封装进行凸块焊接规划，以产生焊盘规划结果; 以及根据所述凸块焊盘规划结果对所述芯片执行第二I / O焊盘放置以产生I / O焊盘放置结果。
-
公开(公告)号：US09379079B1
公开(公告)日：2016-06-28
申请号：US14636137
申请日：2015-03-02
Applicant: MEDIATEK INC.
Inventor： Jia-Wei Fang , Shen-Yu Huang
IPC: H01L23/00 , H01L23/528 , H01L23/488
CPC classification number: H01L23/5283 , H01L24/14 , H01L2224/14131 , H01L2224/14132 , H01L2224/14133 , H01L2224/14135 , H01L2224/14136 , H01L2224/14177 , H01L2224/14179
Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.
Abstract translation: 本发明提供一种倒装芯片方案和一种形成倒装芯片方案。 倒装芯片方案包括：多个凸块，分别以第一图案布置的一些凸块，并且分别以与第一图案不同的第二图案布置的一些凸块; 其中所述第一图案是由三个凸起布置的等边三角形，并且所述第二图案是由四个凸块布置的正方形。 该方法包括：分别以一第一图案布置一些凸块，并分别以与第一图案不同的第二图案布置一些凸块; 其中所述第一图案是由三个凸起布置的等边三角形，并且所述第二图案是由四个凸块布置的正方形。
-
公开(公告)号：US20160126161A1
公开(公告)日：2016-05-05
申请号：US14830727
申请日：2015-08-19
Applicant: MEDIATEK INC.
Inventor： Jia-Wei Fang , Tzu-Hung Lin
IPC: H01L23/48 , H01L25/065 , H01L23/532 , H01L23/498 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49811 , H01L23/3142 , H01L23/481 , H01L23/4824 , H01L23/49838 , H01L23/5226 , H01L23/53228 , H01L24/06 , H01L24/09 , H01L25/065 , H01L25/0655 , H01L2224/0401 , H01L2224/0603 , H01L2224/08235 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/1579
Abstract: A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die assembled on the first surface of the packaging substrate. The semiconductor die includes a plurality of first bump pads and second bump pads on an active surface of the semiconductor die, a plurality of first copper pillars on the first bump pads, and a plurality of second copper pillars on the second bump pads. The first copper pillars have a diameter that is smaller than that of the second copper pillars.
Abstract translation: 半导体封装包括具有第一表面和与第一表面相对的第二表面的封装基板; 以及组装在封装基板的第一表面上的半导体管芯。 半导体管芯包括在半导体管芯的有源表面上的多个第一凸点焊盘和第二凸点焊盘，第一凸点焊盘上的多个第一铜柱和第二凸点焊盘上的多个第二铜柱。 第一个铜柱的直径小于第二个铜柱的直径。
-
Patent Agency Ranking
公开(公告)号：US20220334558A1
公开(公告)日：2022-10-20
申请号：US17490663
申请日：2021-09-30
Applicant: MediaTek Inc.
Inventor： Bo-Jr Huang , Jia-Wei Fang , Jia-Ming Chen , Ya-Ting Chang , Chien-Yuan Lai , Cheng-Yuh Wu , Yi-Pin Lin , Wen-Wen Hsieh , Min-Shu Wang
IPC: G05B19/4155
Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.
-
公开(公告)号：US10109566B2
公开(公告)日：2018-10-23
申请号：US15590021
申请日：2017-05-09
Applicant: MEDIATEK INC.
Inventor： Jia-Wei Fang , Tzu-Hung Lin
IPC: H01L23/00 , H01L23/498 , H01L23/48 , H01L23/31 , H01L23/532 , H01L23/482 , H01L25/065 , H01L23/522
Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.
-
18.发明申请METHOD AND APPARATUS FOR FLIP CHIP PACKAGING CO-DESIGN AND CO-DESIGNED FLIP CHIP PACKAGE 有权用于卷芯片包装的方法和装置共同设计和共同设计的卷筒纸包装公开(公告)号：US20160217244A1
公开(公告)日：2016-07-28
申请号：US15088109
申请日：2016-03-31
Applicant: MEDIATEK INC.
Inventor： Jia-Wei Fang , Shen-Yu Huang
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/40 , G06F2217/78 , H01L24/06 , H01L24/14 , H01L2224/0612 , H01L2224/1412 , H01L2224/73204 , H01L2224/81 , H01L2224/97 , H01L2225/06517 , H01L2924/15311 , H01L2924/00014
Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.
Abstract translation: 本发明提供了一种倒装芯片封装协同设计方法。 该方法包括以下步骤：提供芯片的I / O焊盘信息和PCB的连接信息; 根据芯片的I / O焊盘信息和PCB的连接信息执行第一I / O焊盘放置; 利用RDL路由分析装置对芯片的第一I / O焊盘放置执行凸块焊盘间距分析以产生凸块焊盘间距分析结果; 根据凸点焊盘间距分析结果对封装进行凸块焊接规划，以产生焊盘规划结果; 以及根据所述凸块焊盘规划结果对所述芯片执行第二I / O焊盘放置以产生I / O焊盘放置结果。
-
公开(公告)号：US20160190083A1
公开(公告)日：2016-06-30
申请号：US14636137
申请日：2015-03-02
Applicant: MEDIATEK INC.
Inventor： Jia-Wei Fang , Shen-Yu Huang
IPC: H01L23/00 , H01L23/528
CPC classification number: H01L23/5283 , H01L24/14 , H01L2224/14131 , H01L2224/14132 , H01L2224/14133 , H01L2224/14135 , H01L2224/14136 , H01L2224/14177 , H01L2224/14179
Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.
Abstract translation: 本发明提供一种倒装芯片方案和一种形成倒装芯片方案。 倒装芯片方案包括：多个凸块，分别以第一图案布置的一些凸块，并且分别以与第一图案不同的第二图案布置的一些凸块; 其中所述第一图案是由三个凸起布置的等边三角形，并且所述第二图案是由四个凸块布置的正方形。 该方法包括：分别以一第一图案布置一些凸块，并分别以与第一图案不同的第二图案布置一些凸块; 其中所述第一图案是由三个凸起布置的等边三角形，并且所述第二图案是由四个凸块布置的正方形。
-
公开(公告)号：US09305131B2
公开(公告)日：2016-04-05
申请号：US14535328
申请日：2014-11-07
Applicant: MEDIATEK INC.
Inventor： Jia-Wei Fang , Shen-Yu Huang
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/40 , G06F2217/78 , H01L24/06 , H01L24/14 , H01L2224/0612 , H01L2224/1412 , H01L2224/73204 , H01L2224/81 , H01L2224/97 , H01L2225/06517 , H01L2924/15311 , H01L2924/00014
Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.
Abstract translation: 本发明提供了一种倒装芯片封装协同设计方法。 该方法包括以下步骤：提供芯片的I / O焊盘信息和PCB的连接信息; 根据芯片的I / O焊盘信息和PCB的连接信息执行第一I / O焊盘放置; 利用RDL路由分析装置对芯片的第一I / O焊盘放置执行凸块焊盘间距分析以产生凸块焊盘间距分析结果; 根据凸点焊盘间距分析结果对封装进行凸块焊接规划，以产生焊盘规划结果; 以及根据所述凸块焊盘规划结果对所述芯片执行第二I / O焊盘放置以产生I / O焊盘放置结果。
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.014 seconds)
