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    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION
    11.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION 审中-公开

    公开(公告)号：US20200227427A1

    公开(公告)日：2020-07-16

    申请号：US16834291

    申请日：2020-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

    IPC: H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/66

    Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

    Memory having a continuous channel
    15.
    发明授权
    Memory having a continuous channel 有权

    公开(公告)号：US10224337B2

    公开(公告)日：2019-03-05

    申请号：US15450893

    申请日：2017-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
    18.
    发明申请
    Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells 有权
    形成垂直堆叠记忆单元的综合结构和方法

    公开(公告)号：US20160284719A1

    公开(公告)日：2016-09-29

    申请号：US14666002

    申请日：2015-03-23

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Charles H. Dennison ,  Anish A. Khandekar ,  Brett D. Lowe ,  Lining He ,  Brian Cleereman

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

    Abstract translation: 一些实施例包括形成垂直堆叠的存储单元的方法。 通过交替的绝缘和导电水平的叠层形成开口。 腔体形成为延伸到沿开口侧壁的导电水平。 空腔中的至少一个形成为比空腔中的一个或多个更浅。 在腔内形成电荷阻挡电介质和电荷储存结构。 一些实施例包括具有交替的绝缘和导电水平的叠层的集成结构。 穴位扩展到导电水平。 至少一个空腔比空腔中的一个或多个其它孔更浅，至少约2纳米。 电荷阻挡电介质位于空腔内。 电荷存储结构位于空腔内。

    Methods and apparatuses having memory cells including a monolithic semiconductor channel
    19.
    发明授权
    Methods and apparatuses having memory cells including a monolithic semiconductor channel 有权
    具有包括单片半导体通道的存储单元的方法和装置

    公开(公告)号：US09431410B2

    公开(公告)日：2016-08-30

    申请号：US14069574

    申请日：2013-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

    IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66

    CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

    Abstract translation: 公开了形成一串存储单元的方法，具有一串存储单元的装置和系统。 用于形成一串存储单元的一种这样的方法在衬底上形成源材料。 可以在源材料上形成封盖材料。 可以在封盖材料之上形成选择栅极材料。 多个电荷存储结构可以在选择栅极材料上以多个交替层级的控制栅极和绝缘体材料形成。 可以通过控制栅极和绝缘体材料，选择栅极材料和封盖材料的多个交替层级形成第一开口。 通道材料可以沿着第一开口的侧壁形成。 通道材料的厚度小于第一开口的宽度，使得第二开口由半导体沟道材料形成。

    Memory Arrays and Methods of Fabricating Integrated Structures
    20.
    发明申请
    Memory Arrays and Methods of Fabricating Integrated Structures 有权
    内存阵列和制造集成结构的方法

    公开(公告)号：US20160172373A1

    公开(公告)日：2016-06-16

    申请号：US15049097

    申请日：2016-02-21

    Applicant: Micron Technology, Inc.

    Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

    Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

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