公开(公告)号：US20180101427A1

公开(公告)日：2018-04-12

申请号：US15840610

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Jae-Kwan Park

IPC: G06F11/07 ,  G11C7/06 ,  G11C29/24 ,  G11C7/10

CPC classification number: G06F11/079 ,  G06F11/0727 ,  G06F11/0751 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/1063 ,  G11C29/24 ,  G11C2207/063

Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

公开(公告)号：US20170270983A1

公开(公告)日：2017-09-21

申请号：US15614072

申请日：2017-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Viloante Moschiano ,  Michele Incarnati ,  Luca de Santis

IPC: G11C7/22 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

公开(公告)号：US09530470B2

公开(公告)日：2016-12-27

申请号：US14705717

申请日：2015-05-06

Applicant: Micron Technology, Inc.

Inventor： Jae-Kwan Park

IPC: G11C7/12 ,  G11C16/28 ,  G11C7/14 ,  G11C16/24

CPC classification number: G11C7/12 ,  G11C7/14 ,  G11C16/06 ,  G11C16/24 ,  G11C16/28

Abstract: Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference.

公开(公告)号：US20150213848A1

公开(公告)日：2015-07-30

申请号：US14165389

申请日：2014-01-27

Applicant: Micron Technology, Inc.

Inventor： Jae-Kwan Park

IPC: G11C7/10

CPC classification number: G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3427

Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.

Abstract translation: 描述用于提供响应于电压确定的程序电压的装置和方法。 示例性装置包括包括多个接入线的存储器阵列。 该示例设备还包括耦合到存储器阵列的存储器存取电路。 存储器访问电路被配置为在存储器编程操作期间向多个接入线路提供禁止电压。 存储器访问电路还被配置为在存储器程序操作期间，响应于确定多个访问线路的访问线路具有等于或等于的电压的确定，在多个访问线路中的目标访问线路上提供编程电压 大于阈值电压。 阈值电压小于抑制电压。

公开(公告)号：US11955204B2

公开(公告)日：2024-04-09

申请号：US17959078

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

IPC: G06F3/06 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

公开(公告)号：US10366728B2

公开(公告)日：2019-07-30

申请号：US15910375

申请日：2018-03-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jae-Kwan Park

IPC: G11C16/08 ,  G11C7/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.

公开(公告)号：US20180366203A1

公开(公告)日：2018-12-20

申请号：US16111319

申请日：2018-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/30 ,  G11C16/24 ,  G11C16/04 ,  G11C7/04 ,  G11C5/14

CPC classification number: G11C16/26 ,  G11C5/145 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatus and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US10127988B2

公开(公告)日：2018-11-13

申请号：US15248692

申请日：2016-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C7/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/14

Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US20180061497A1

公开(公告)日：2018-03-01

申请号：US15248692

申请日：2016-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C7/04 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C5/145 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32

Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US10790029B2

公开(公告)日：2020-09-29

申请号：US16111319

申请日：2018-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C7/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/14

Abstract: Apparatus and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.