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    Intra-controllers for error correction code
    12.
    发明授权
    Intra-controllers for error correction code 有权

    公开(公告)号：US12222803B2

    公开(公告)日：2025-02-11

    申请号：US18216254

    申请日：2023-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  John D. Porter

    IPC: G06F11/10

    Abstract: An on-die controller can provide an error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller eliminates a need to transfer error correction code (ECC) data to an external controller that may have provided the error correction capability in lieu of the on-die controller, which can provide more channel bandwidth for other types of non-user data for further strengthening data reliability, security, integrity of the memory system.

    MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
    13.
    发明申请
    MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY 有权

    公开(公告)号：US20240395303A1

    公开(公告)日：2024-11-28

    申请号：US18794453

    申请日：2024-08-05

    Applicant: Micron Technology, Inc.

    Inventor： Si Hong Kim ,  John D. Porter

    IPC: G11C11/22

    Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.

    Wear leveling
    15.
    发明授权
    Wear leveling 有权

    公开(公告)号：US11646065B2

    公开(公告)日：2023-05-09

    申请号：US17367060

    申请日：2021-07-02

    Applicant: Micron Technology, Inc.

    Inventor： John D. Porter

    IPC: G11C7/10 ,  G06F12/02 ,  G11C11/22

    CPC classification number: G11C7/1042 ,  G06F12/0246 ,  G11C7/1039 ,  G06F2212/7211 ,  G11C11/221 ,  G11C2207/2236

    Abstract: An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.

    Apparatuses and methods for plate coupled sense amplifiers
    16.
    发明授权
    Apparatuses and methods for plate coupled sense amplifiers 有权

    公开(公告)号：US10699755B2

    公开(公告)日：2020-06-30

    申请号：US16134732

    申请日：2018-09-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Adam S. El-Mansouri ,  John D. Porter

    IPC: G11C7/06 ,  G11C11/22 ,  G11C5/14 ,  G11C7/22

    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.

    Apparatus and methods of driving signal for reducing the leakage current
    18.
    发明授权
    Apparatus and methods of driving signal for reducing the leakage current 有权
    驱动信号以减少漏电流的装置和方法

    公开(公告)号：US09054700B2

    公开(公告)日：2015-06-09

    申请号：US14223647

    申请日：2014-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Gi-Hong Kim ,  John D. Porter

    IPC: G11C8/00 ,  G11C11/34 ,  H03K17/16 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/419

    CPC classification number: H03K17/162 ,  G11C7/1057 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/419

    Abstract: Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor.

    Abstract translation: 公开了用于驱动信号的装置和方法。 示例性设备包括预驱动器电路和驱动器电路。 预驱动器电路包括降压晶体管，并且驱动器电路包括被配置为耦合到参考电压的下拉晶体管。 在第一模式中，降压晶体管被配置为将提供给下拉晶体管的电压降低到小于电源电压，并且在第二模式中，降压晶体管被配置为提供电源电压 到下拉晶体管。 示例性信号驱动器电路的预驱动器电路还可以包括升压晶体管，其被配置为将提供给驱动器电路的上拉晶体管的电压增加到大于参考电压，并且在第二模式中，步骤 该晶体管被配置为向上拉晶体管提供参考电压的电压。

    MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
    19.
    发明公开
    MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY 审中-公开

    公开(公告)号：US20240071456A1

    公开(公告)日：2024-02-29

    申请号：US17899859

    申请日：2022-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Si Hong Kim ,  John D. Porter

    IPC: G11C11/22

    CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2257

    Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.

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