公开(公告)号：US11990199B2

公开(公告)日：2024-05-21

申请号：US17647152

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Kang-Yong Kim

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/4401

Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

公开(公告)号：US20240161796A1

公开(公告)日：2024-05-16

申请号：US18420404

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

CPC classification number: G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US20240079036A1

公开(公告)日：2024-03-07

申请号：US17930034

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  Kang-Yong Kim

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/023 ,  G06F13/1668 ,  G06F2212/1016

Abstract: Apparatuses and techniques for implementing a standalone mode are described. The standalone mode refers to a mode in which a die that is designed to operate as one of multiple dies that are interconnected can operate independently of another one of the multiple dies. Prior to connecting the die to the other die, the die can perform a standalone read operation and/or a standalone write operation in accordance with the standalone mode. In this way, testing (or debugging) can be performed during an earlier stage in the manufacturing process before integrating the die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the standalone mode can be executed independent of whether the die is connected to the other die.

公开(公告)号：US20240078041A1

公开(公告)日：2024-03-07

申请号：US17930044

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0614 ,  G06F3/0673 ,  G06F12/0223

Abstract: This document describes apparatuses and techniques for die-based rank management for a memory system. In various aspects, a die-based rank controller (controller) can determine which memory dies of a memory device are not functional to store data and correlate rank selections of a memory system to ranks of other memory dies (e.g., functional memory dies). The controller may store information that indicates the correlation or mapping of the rank selections to the ranks of the other memory dies to enable access to those ranks of the memory system. In some aspects, the controller receives a command to access the memory device with a rank selection, and the controller enables access to a corresponding rank based on the information. By so doing, aspects of die-based rank management enable memory packages with non-functional memory dies to be used instead of discarded, which can increase production utilization or lower manufacturing costs.

公开(公告)号：US11869626B2

公开(公告)日：2024-01-09

申请号：US17502792

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyunyoo Lee

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1066 ,  G11C7/1093

Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

公开(公告)号：US11868650B2

公开(公告)日：2024-01-09

申请号：US17662993

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G06F3/00 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4096 ,  G11C2211/4062

Abstract: Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first emphasized characteristic and a second memory circuit having a second emphasized characteristic. The first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.

公开(公告)号：US11783885B2

公开(公告)日：2023-10-10

申请号：US17513090

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C7/1009 ,  G11C11/40618 ,  G11C11/40622

Abstract: Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM), and an associated host device are described. The memory device includes control circuitry that can determine an operational status of the memory device (e.g., whether the memory device is currently performing a self-refresh operation). The control circuitry can also transmit a signal indicative of the operational status to the host device in response to receiving a command directing the memory device to exit a self-refresh mode. The host device can operate based on the signal. The signal may therefore allow the memory device, the host device, or both to manage operations, including whether to send, receive, or process commands and data read/write requests during times that may be associated with self-refresh operations.

公开(公告)号：US11783883B2

公开(公告)日：2023-10-10

申请号：US17459446

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G11C11/00 ,  G11C11/406

CPC classification number: G11C11/40615

Abstract: Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device and the host device can include control logic that enables the host device to transmit a burst value to the memory device, which may enable the memory device, the host, or both, to manage refresh operations during a normal operation mode or a self-refresh mode. The burst value can be transmitted to the memory device in association with a command (e.g., a command directing the memory device to enter the self-refresh mode). The burst value can specify a number of self-refresh operations to be initiated at the memory device in response to receiving the command. When the specified number of self-refresh operations are completed, regular self-refresh operations may begin, with an internal self-refresh timer counting an interval to the next self-refresh operation.

公开(公告)号：US11644985B2

公开(公告)日：2023-05-09

申请号：US16838873

申请日：2020-04-02

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0625 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0238 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.

公开(公告)号：US20220334986A1

公开(公告)日：2022-10-20

申请号：US17751298

申请日：2022-05-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.