公开(公告)号：US20230397424A1

公开(公告)日：2023-12-07

申请号：US18324084

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Everett A. McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Christopher R. Ritchie ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Sijia Yu ,  Naiming Liu

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure, a memory pillar, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and defines memory cells at intersections of the memory pillar and the conductive structures. The boron-containing material is on at least a portion of the conductive structures of the stack structure. Related methods and electronic systems are also described.

公开(公告)号：US20230395149A1

公开(公告)日：2023-12-07

申请号：US17851865

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  David Ross Economy ,  John D. Hopkins ,  Nancy M. Lomeli ,  Jiewei Chen ,  Rita J. Klein ,  Everett A. McTeer ,  Aaron P. Thurber

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11800706B2

公开(公告)日：2023-10-24

申请号：US17395751

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout ,  Rita J. Klein

IPC: H10B41/41 ,  G11C5/06 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C5/063 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11594495B2

公开(公告)日：2023-02-28

申请号：US17209993

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  G11C5/06 ,  G11C5/02 ,  H01L27/06

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220254727A1

公开(公告)日：2022-08-11

申请号：US17660669

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US11244903B2

公开(公告)日：2022-02-08

申请号：US16730505

申请日：2019-12-30

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Travis Rampton ,  Everett Allen McTeer ,  Rita J. Klein

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528

Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.

公开(公告)号：US20210287990A1

公开(公告)日：2021-09-16

申请号：US16820046

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Luca Fumagalli ,  John D. Hopkins ,  Rita J. Klein ,  Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A microelectronic device comprises a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20210287989A1

公开(公告)日：2021-09-16

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulating structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and comprise beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11056507B2

公开(公告)日：2021-07-06

申请号：US16927084

申请日：2020-07-13

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Rita J. Klein

IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

公开(公告)号：US20210202388A1

公开(公告)日：2021-07-01

申请号：US16730505

申请日：2019-12-30

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Travis Rampton ,  Everett Allen McTeer ,  Rita J. Klein

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.