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公开(公告)号：US10311919B2
公开(公告)日：2019-06-04
申请号：US15662059
申请日：2017-07-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Stefan Frederik Schippers
Abstract: Apparatuses and methods for calibrating sense amplifiers in a semiconductor memory are disclosed. An example apparatus includes an amplifier circuit and a calibration circuit. The amplifier circuit is configured to be coupled to a supply voltage and a reference voltage, and when activated the amplifier circuit is configured to provide an output signal at an output that is complementary to an input signal provided to an input. When activated by a calibration signal, the calibration circuit is configured to provide a calibration voltage to the output of the amplifier circuit, wherein the calibration voltage is an equilibration voltage between the supply voltage and the reference voltage provided to the amplifier circuit.
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公开(公告)号：US11205469B2
公开(公告)日：2021-12-21
申请号：US16509916
申请日：2019-07-12
Applicant: Micron Technology, Inc.
IPC: G06F1/3296 , G11C11/4074 , G11C11/406
Abstract: Methods, systems, and devices for power domain switches for switching power reduction are described. A device, such as a memory device, may receive an indication (e.g., a command) for a power domain component of the device to transition between states. The device may float first and second gate drivers. A pass gate may be used to connect (e.g., short) the first switch to the second switch. The pass gate may be deactivated to isolate the gates. The first and second gate drivers may be enabled, and the first and second gate drivers drive the first and second switches to disconnect the power domain component from a power source to deactivate the power domain component, or connect to the power source to activate the power domain component. The energy to switch between active and inactive states may thereby be reduced.
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公开(公告)号：US11062763B2
公开(公告)日：2021-07-13
申请号：US16379222
申请日：2019-04-09
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Stefan Frederik Schippers
IPC: G11C11/24 , G11C11/4096 , G11C11/4091 , G11C11/408 , H01L27/108 , G11C11/56
Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
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公开(公告)号：US10937487B2
公开(公告)日：2021-03-02
申请号：US16854239
申请日：2020-04-21
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Stefan Frederik Schippers , Xinwei Guo
IPC: G11C11/24 , G11C11/4091 , G11C11/408 , H03F3/45 , G11C11/22
Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
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公开(公告)号：US10672457B2
公开(公告)日：2020-06-02
申请号：US16453208
申请日：2019-06-26
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Stefan Frederik Schippers , Xinwei Guo
IPC: G11C11/24 , G11C11/4091 , G11C11/408 , H03F3/45 , G11C11/22
Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
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Patent Agency Ranking
公开(公告)号：US20190279689A1
公开(公告)日：2019-09-12
申请号：US16426435
申请日：2019-05-30
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Stefano Ratti , Gary G. Lazarowics , Stefan Frederik Schippers , Stefano Claudio Roseghini , Angelo Clemente Scardilla
Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.
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公开(公告)号：US20240237358A1
公开(公告)日：2024-07-11
申请号：US18407074
申请日：2024-01-08
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Corrado Villa , Stefan Frederik Schippers , Efrem Bolandrina
CPC classification number: H10B63/34 , G11C13/0004 , G11C13/003 , H10B63/845 , G11C2213/71 , G11C2213/79
Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.
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公开(公告)号：US11900989B2
公开(公告)日：2024-02-13
申请号：US17370488
申请日：2021-07-08
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Stefan Frederik Schippers
IPC: G11C11/40 , G11C11/4096 , G11C11/4091 , G11C11/408 , H10B12/00 , G11C11/56
CPC classification number: G11C11/4096 , G11C11/4085 , G11C11/4091 , H10B12/30 , H10B12/50 , G11C11/4087 , G11C11/565
Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
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公开(公告)号：US11877457B2
公开(公告)日：2024-01-16
申请号：US16976411
申请日：2020-05-25
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Corrado Villa , Stefan Frederik Schippers , Efrem Bolandrina
CPC classification number: H10B63/34 , G11C13/003 , G11C13/0004 , H10B63/845 , G11C2213/71 , G11C2213/79
Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.
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公开(公告)号：US20210012827A1
公开(公告)日：2021-01-14
申请号：US16509916
申请日：2019-07-12
Applicant: Micron Technology, Inc.
IPC: G11C11/4074 , G06F1/3296 , G11C11/406
Abstract: Methods, systems, and devices for power domain switches for switching power reduction are described. A device, such as a memory device, may receive an indication (e.g., a command) for a power domain component of the device to transition between states. The device may float first and second gate drivers. A pass gate may be used to connect (e.g., short) the first switch to the second switch. The pass gate may be deactivated to isolate the gates. The first and second gate drivers may be enabled, and the first and second gate drivers drive the first and second switches to disconnect the power domain component from a power source to deactivate the power domain component, or connect to the power source to activate the power domain component. The energy to switch between active and inactive states may thereby be reduced.
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