公开(公告)号：US20160180934A1

公开(公告)日：2016-06-23

申请号：US14971634

申请日：2015-12-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Takehiro Hasegawa ,  Mark Helm

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 本文公开的各种实施例包括通过响应于流过所选择的串的读取电流到数据线来感测逻辑电平来读取所选择的存储器串中的所选择的存储器单元中的逻辑电平的装置和方法。 公开了附加装置，系统和方法。

公开(公告)号：US09252148B2

公开(公告)日：2016-02-02

申请号：US14161170

申请日：2014-01-22

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Koji Sakui

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  G11C5/14

CPC classification number: H01L27/11531 ,  G11C5/145 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0694 ,  H01L27/115 ,  H01L27/11546 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66477 ,  H01L29/78

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

Abstract translation: 已经公开了装置和方法。 一种这样的设备包括形成在基板的顶侧上的一系列存储单元。 支撑电路形成在衬底的背面，并通过衬底中的垂直互连耦合到存储器单元串。 垂直互连可以是诸如环绕衬底晶体管和/或环绕栅极晶体管的晶体管。

公开(公告)号：US20230029528A1

公开(公告)日：2023-02-02

申请号：US17385340

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Chikara Kondo ,  Yuan He ,  Hyunui Lee

IPC: G11C29/12 ,  G11C7/22

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a data signal according to a clock signal to obtain a data sample; sampling the data signal according to an advanced clock signal to obtain an advanced data sample; and sampling the data signal according to a delayed clock signal to obtain a delayed data sample. The method may also include comparing the data sample with the advanced data sample and the delayed data sample and performing an action based on the comparison. The action may include selecting a data sample, selecting a clock signal and/or adjusting a clock signal. Associated devices and systems are also disclosed.

公开(公告)号：US11551746B2

公开(公告)日：2023-01-10

申请号：US16953214

申请日：2020-11-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Daigo Toyama ,  Chikara Kondo ,  Takehiro Hasegawa

IPC: G11C7/12 ,  G11C11/4097 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F3/06

Abstract: Apparatuses, systems, and methods for faster memory access regions. A memory array may have a first bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.

公开(公告)号：US20220157372A1

公开(公告)日：2022-05-19

申请号：US16953214

申请日：2020-11-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Daigo Toyama ,  Chikara Kondo ,  Takehiro Hasegawa

IPC: G11C11/4097 ,  G11C11/4091

Abstract: Apparatuses, systems, and methods for faster memory access regions. A memory array may have a fiat bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.

公开(公告)号：US10910389B2

公开(公告)日：2021-02-02

申请号：US16418743

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Koji Sakui

IPC: G11C16/04 ,  H01L27/11531 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  H01L21/28 ,  H01L27/06 ,  H01L27/11546 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  G11C5/14

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

公开(公告)号：US10319729B2

公开(公告)日：2019-06-11

申请号：US15011819

申请日：2016-02-01

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Koji Sakui

IPC: H01L21/8238 ,  H01L27/11531 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  G11C16/04 ,  H01L27/06 ,  H01L27/11546 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/28 ,  G11C5/14

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

公开(公告)号：US20160148943A1

公开(公告)日：2016-05-26

申请号：US15011819

申请日：2016-02-01

Applicant: Micron Technology, Inc.

Inventor： Takehiro Hasegawa ,  Koji Sakui

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11531 ,  G11C5/145 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0694 ,  H01L27/115 ,  H01L27/11546 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66477 ,  H01L29/78

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.