公开(公告)号：US20230027926A1

公开(公告)日：2023-01-26

申请号：US17381860

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Shindeok Kang ,  Timothy M. Hollis ,  Dragos Dimitriu

IPC: G11C11/56 ,  G11C7/02

Abstract: Methods, systems, and devices related to an improved driver for non-binary signaling are described. A driver for a signal line may include a set of drivers of a first type and a set of drivers of a second type. When the driver drives the signal line using multiple drivers of the first type, at least one additional driver of the first type may compensate for non-linearities associated with one or more other drivers of the first type, which may have been calibrated at other voltages. The at least one additional driver of the first type may be calibrated for use at a particular voltage, to compensate for non-linearities associated with the one or more other drivers of the first type as exhibited at that particular voltage.

公开(公告)号：US20230006866A1

公开(公告)日：2023-01-05

申请号：US17874939

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H04L25/03

Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.

公开(公告)号：US11508422B2

公开(公告)日：2022-11-22

申请号：US16530739

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Chan H. Yoo ,  Randon K. Richards ,  Timothy M. Hollis

IPC: G11C7/22 ,  G11C16/10 ,  G11C7/10

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

公开(公告)号：US11450380B2

公开(公告)日：2022-09-20

申请号：US16940194

申请日：2020-07-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： M. Ataul Karim ,  Timothy M. Hollis

IPC: G11C11/24 ,  G11C11/4093 ,  H04L27/08 ,  G11C11/56

Abstract: Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

公开(公告)号：US20220004317A1

公开(公告)日：2022-01-06

申请号：US17360943

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US20210383849A1

公开(公告)日：2021-12-09

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11088895B2

公开(公告)日：2021-08-10

申请号：US16881337

申请日：2020-05-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean Gans ,  Randon Richards ,  Bruce W. Schober

IPC: G06F13/00 ,  H04L12/24 ,  H04L12/863 ,  G11C7/10 ,  H04L25/03 ,  G11C7/22 ,  G11C5/04

Abstract: According to one embodiment, a data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

公开(公告)号：US10861531B2

公开(公告)日：2020-12-08

申请号：US16375770

申请日：2019-04-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dragos Dimitriu

IPC: G11C7/22 ,  G11C11/4074 ,  G11C7/10 ,  G11C8/06 ,  G11C11/4096 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076

Abstract: Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other.

公开(公告)号：US10832748B2

公开(公告)日：2020-11-10

申请号：US16666045

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C8/12 ,  G06F12/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4093

Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

公开(公告)号：US20200233741A1

公开(公告)日：2020-07-23

申请号：US16744025

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Martin Brox ,  Peter Mayer ,  Wolfgang Anton Spirki ,  Thomas Hein ,  Michael Dieter Richter ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F11/10 ,  G06F12/02 ,  G06F11/16

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.