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    PHASE CHANGE MEMORY APPARATUSES AND METHODS OF FORMING SUCH APPARATUSES
    11.
    发明申请
    PHASE CHANGE MEMORY APPARATUSES AND METHODS OF FORMING SUCH APPARATUSES 有权
    相变记忆装置和形成这种装置的方法

    公开(公告)号：US20150340408A1

    公开(公告)日：2015-11-26

    申请号：US14285286

    申请日：2014-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

    Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between the memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

    Abstract translation: 相变存储装置包括存储单元，其包括相变材料，电耦合到至少一些存储单元的对准组的位线以及电耦合到存储单元的相变材料的加热元件。 加热元件包括沿位线方向延伸的垂直部分。 附加的相变存储装置包括位于存储器列和基极接触柱之间的虚拟列。 虚拟列包括相变存储单元，并且没有耦合到其相变存储单元的加热元件。 附加的相变存储装置包括可操作地耦合到相变存储器单元的加热元件。 加热元件和相变存储器单元之间的界面面积具有与位线宽度无关的长度。 方法涉及形成这种相变存储装置。

    Memory Cells, Integrated Devices, and Methods of Forming Memory Cells
    12.
    发明申请
    Memory Cells, Integrated Devices, and Methods of Forming Memory Cells 有权
    记忆单元，集成器件和形成存储器单元的方法

    公开(公告)号：US20140206171A1

    公开(公告)日：2014-07-24

    申请号：US14225111

    申请日：2014-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Ugo Russo ,  Agostino Pirovano ,  Simone Lavizzari

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675

    Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.

    Abstract translation: 一些实施例包括集成设备，诸如存储器单元。 这些装置可以包括硫族化物材料，在硫族化物材料上的导电材料，以及在导电材料和硫族化物材料之间的散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。 一些实施例包括形成存储器单元的方法。 可以在加热器材料上形成硫族化物材料。 可以在硫族化物材料上形成导电材料。 可以在导电材料和硫族化物材料之间形成散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。

    Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming Assemblies
    18.
    发明申请
    Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming Assemblies 有权

    公开(公告)号：US20220037346A1

    公开(公告)日：2022-02-03

    申请号：US17499218

    申请日：2021-10-12

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo

    IPC: H01L27/11556 ,  H01L27/11521 ,  G11C8/12

    Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.

    Void formation in charge trap structures
    19.
    发明授权
    Void formation in charge trap structures 有权

    公开(公告)号：US11037951B2

    公开(公告)日：2021-06-15

    申请号：US16580751

    申请日：2019-09-24

    Applicant: Micron Technology, Inc.

    Inventor： Chris M. Carlson ,  Ugo Russo

    IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/51

    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

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