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公开(公告)号：US10770435B2
公开(公告)日：2020-09-08
申请号：US16459394
申请日：2019-07-01
Applicant: Micron Technology, Inc.
Inventor： Sameer S. Vadhavkar , Xiao Li , Anilkumar Chandolu
IPC: H01L23/31 , H01L25/065 , H01L23/367
Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
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12.发明授权公开(公告)号：US10741468B2
公开(公告)日：2020-08-11
申请号：US16229257
申请日：2018-12-21
Applicant: Micron Technology, Inc.
Inventor： Steven K. Groothuis , Jian Li , Haojun Zhang , Paul A. Silvestri , Xiao Li , Shijian Luo , Luke G. England , Brent Keeth , Jaspreet S. Gandhi
IPC: H01L23/36 , H01L23/367 , H01L23/42 , H01L25/00 , H01L25/065 , H01L25/18 , H01L23/373
Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
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13.发明申请公开(公告)号：US20190006321A1
公开(公告)日：2019-01-03
申请号：US16106190
申请日：2018-08-21
Applicant: Micron Technology, Inc.
Inventor： Bradley R. Bitz , Xiao Li
IPC: H01L25/065 , H01L23/367 , H01L21/56 , H01L23/31 , H01L21/48 , H01L25/00
Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.
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公开(公告)号：US10074633B2
公开(公告)日：2018-09-11
申请号：US15345973
申请日：2016-11-08
Applicant: Micron Technology, Inc.
Inventor： Bradley R. Bitz , Xiao Li
IPC: H01L21/56 , H01L25/065 , H01L23/31 , H01L25/00 , H01L21/48
CPC classification number: H01L25/0657 , H01L21/4882 , H01L21/563 , H01L21/565 , H01L23/3121 , H01L23/3128 , H01L23/367 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06586 , H01L2225/06589 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/16251
Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.
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公开(公告)号：US09960150B2
公开(公告)日：2018-05-01
申请号：US15181212
申请日：2016-06-13
Applicant: Micron Technology, Inc.
Inventor： Bradley R. Bitz , Xiao Li , Jaspreet S. Gandhi
IPC: H01L25/065 , H01L23/427 , H01L23/46 , H01L23/473 , H01L23/42
CPC classification number: H01L25/0657 , H01L23/42 , H01L23/427 , H01L23/46 , H01L23/473 , H01L2224/16145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589
Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.
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Patent Agency Ranking
公开(公告)号：US20170358556A1
公开(公告)日：2017-12-14
申请号：US15181212
申请日：2016-06-13
Applicant: Micron Technology, Inc.
Inventor： Bradley R. Bitz , Xiao Li , Jaspreet S. Gandhi
IPC: H01L25/065 , H01L23/473 , H01L23/42 , H01L23/46 , H01L23/427
CPC classification number: H01L25/0657 , H01L23/42 , H01L23/427 , H01L23/46 , H01L23/473 , H01L2224/16145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589
Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.
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17.发明授权公开(公告)号：US09837396B2
公开(公告)日：2017-12-05
申请号：US15254586
申请日：2016-09-01
Applicant: Micron Technology, Inc.
Inventor： Sameer S. Vadhavkar , Xiao Li , Steven K. Groothuis , Jian Li , Jaspreet S. Gandhi , James M. Derderian , David R. Hembree
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L25/00 , H01L25/065 , H01L25/16 , H01L21/56 , H01L23/04 , H01L21/50 , H01L23/36 , H01L23/367 , H01L21/48
CPC classification number: H01L25/50 , H01L21/4882 , H01L21/50 , H01L21/563 , H01L23/04 , H01L23/36 , H01L23/3675 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L2224/16145 , H01L2225/06568 , H01L2225/06589
Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
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18.发明授权Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods 有权具有高效热路径和相关方法的堆叠式半导体管芯组件公开(公告)号：US09443744B2
公开(公告)日：2016-09-13
申请号：US14330934
申请日：2014-07-14
Applicant: Micron Technology, Inc.
Inventor： Sameer S. Vadhavkar , Xiao Li , Steven K. Groothuis , Jian Li , Jaspreet S. Gandhi , James M. Derderian , David R. Hembree
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L21/56 , H01L25/065 , H01L25/16 , H01L25/00 , H01L23/04 , H01L21/50 , H01L23/36 , H01L23/367 , H01L21/48
CPC classification number: H01L25/50 , H01L21/4882 , H01L21/50 , H01L21/563 , H01L23/04 , H01L23/36 , H01L23/3675 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L2224/16145 , H01L2225/06568 , H01L2225/06589
Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，具有周边区域和堆叠区域的第一半导体管芯，以及附接到第一管芯的堆叠区域的第二半导体管芯，使得外围区域是 第二次死亡 组件还包括热传递单元，其具有附接到第一模具的周边区域的基座，通过粘合剂附接到基座的盖子以及至少由盖子限定的空腔，其中第二模具在空腔内。 组件还包括在腔中的底部填充物，其中底部填充物的圆角部分沿着基脚的一部分向上延伸一段距离，并沿基部的至少一部分向上延伸。
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19.发明申请STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED METHODS 有权堆叠式半导体组件，具有高效率热性能和相关方法公开(公告)号：US20160013115A1
公开(公告)日：2016-01-14
申请号：US14330934
申请日：2014-07-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sameer S. Vadhavkar , Xiao Li , Steven K. Groothuis , Jian Li , Jaspreet S. Gandhi , James M. Derderian , David R. Hembree
CPC classification number: H01L25/50 , H01L21/4882 , H01L21/50 , H01L21/563 , H01L23/04 , H01L23/36 , H01L23/3675 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L2224/16145 , H01L2225/06568 , H01L2225/06589
Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，具有周边区域和堆叠区域的第一半导体管芯，以及附接到第一管芯的堆叠区域的第二半导体管芯，使得外围区域是 第二次死亡 组件还包括热传递单元，其具有附接到第一模具的周边区域的基座，通过粘合剂附接到基座的盖子以及至少由盖子限定的空腔，其中第二模具在空腔内。 组件还包括在腔中的底部填充物，其中底部填充物的圆角部分沿着基脚的一部分向上延伸一段距离，并沿基部的至少一部分向上延伸。
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公开(公告)号：US20130299868A1
公开(公告)日：2013-11-14
申请号：US13944399
申请日：2013-07-17
Applicant: Micron Technology, Inc.
Inventor： Owen Fay , Xiao Li , Josh Woodland , Shijian Luo , Jaspreet Gandhi , Te-Sung Wu
IPC: H01L33/62
CPC classification number: H01L33/62 , H01L24/29 , H01L24/83 , H01L24/94 , H01L33/0079 , H01L33/0095 , H01L2224/83193 , H01L2224/8381 , H01L2224/83825 , H01L2224/94 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2224/83 , H01L2924/00
Abstract: Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner.
Abstract translation: 描述了包括LED器件在内的器件形成方法。 装置可以包括氟化化合物层。 所述的方法可以利用等离子体处理来形成氟化化合物层。 所描述的方法可以操作以产生金属间化合物层，其以相对有效和廉价的方式将诸如半导体晶片的两个基板结合在一起。
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