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公开(公告)号：US09520199B2
公开(公告)日：2016-12-13
申请号：US14692927
申请日：2015-04-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuo-Pin Chang
CPC classification number: G11C16/0483 , G11C7/18 , G11C16/0433 , G11C16/28 , G11C16/3427 , H01L27/11582
Abstract: A memory device includes: a plurality of conductive stacked structures including at least a string select line, a plurality of word lines and at least a ground select line; a plurality of memory cells formed in the conductive stacked structures; a plurality of bit lines, formed on the conductive stacked structures; and at least an odd common source line and at least an even common source line, formed on the conductive stacked structures. The odd common source line is coupled to a plurality of odd bit lines of the bit lines. The even common source line is coupled to a plurality of even bit lines of the bit lines.
Abstract translation: 存储器件包括：至少包括串选择线，多个字线和至少一地选线的多个导电堆叠结构; 形成在所述导电堆叠结构中的多个存储单元; 多个位线，形成在导电堆叠结构上; 以及形成在导电堆叠结构上的至少一个奇数公共源极线和至少一个偶数公共源极线。 奇数公共源极线耦合到位线的多个奇数位线。 偶数公共源极线耦合到位线的多个偶数位线。
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公开(公告)号：US20160300617A1
公开(公告)日：2016-10-13
申请号：US14684561
申请日：2015-04-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hung-Sheng Chang , Chih-Chang Hsieh , Kuo-Pin Chang
IPC: G11C16/16
Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.
Abstract translation: 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。
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公开(公告)号：US09466384B1
公开(公告)日：2016-10-11
申请号：US14684561
申请日：2015-04-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hung-Sheng Chang , Chih-Chang Hsieh , Kuo-Pin Chang
Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.
Abstract translation: 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。
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公开(公告)号：US09171636B2
公开(公告)日：2015-10-27
申请号：US13940010
申请日：2013-07-11
Applicant: Macronix International Co., Ltd.
Inventor： Kuo-Pin Chang , Wen-Wei Yeh , Chih-Shen Chang , Hang-Ting Lue
CPC classification number: G11C16/3459 , G11C16/3427
Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.
Abstract translation: 描述了一种存储器件，其包括具有由多个字线访问的多个级别的存储器单元的存储器单元的三维阵列以及多个位线。 控制电路耦合到多个字线和多个位线。 控制电路适用于通过热载流子生成辅助FN隧道在阵列的选定电平和所选择的字线上对选定的存储单元进行编程，同时抑制未选择的电平和所选电平中的未选定存储单元的干扰 未经选择的字线通过自我提升。
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公开(公告)号：US10593697B1
公开(公告)日：2020-03-17
申请号：US16540275
申请日：2019-08-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chih-Wei Hu , Teng-Hao Yeh , Yu-Wei Jiang , Kuo-Pin Chang
IPC: H01L27/11582 , H01L27/1157
Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.
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Patent Agency Ranking
公开(公告)号：US09747989B1
公开(公告)日：2017-08-29
申请号：US15410815
申请日：2017-01-20
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuo-Pin Chang
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/08 , G11C16/3418
Abstract: A memory device and a control method of the memory device are provided. The memory device includes a decoding circuit, Q switching circuits and Q blocks. The decoding circuit generates Q select signals. A k-th select signal of the Q select signals has a first select voltage. The other (Q−1) select signals have a second select voltage. The Q switching circuits receive an erase voltage, and generate Q common source line signals according to the Q select signals. A k-th common source line signal of the Q common source line signals generated by a k-th switching circuit of the Q switching circuits has the erase voltage. The Q blocks receive the Q common source line signals, respectively. A k-th block of the Q blocks is erased according to the k-th common source line signal.
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公开(公告)号：US09685233B2
公开(公告)日：2017-06-20
申请号：US14153934
申请日：2014-01-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chih-Chang Hsieh , Ti-Wen Chen , Yung Chun Li , Kuo-Pin Chang
IPC: G11C16/10 , G11C11/56 , G11C16/34 , G11C16/04 , H01L27/11551 , H01L27/11578
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5621 , G11C2216/14 , H01L27/11551 , H01L27/11578
Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.
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公开(公告)号：US09620217B2
公开(公告)日：2017-04-11
申请号：US14668790
申请日：2015-03-25
Applicant: Macronix International Co., Ltd.
Inventor： Hang-Ting Lue , Kuo-Pin Chang
IPC: G11C16/14 , G11C16/08 , G11C16/04 , G11C16/16 , H01L27/11551 , H01L27/11578
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/16 , G11C2216/18 , H01L27/11551 , H01L27/11578
Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.
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公开(公告)号：US09530503B2
公开(公告)日：2016-12-27
申请号：US14723321
申请日：2015-05-27
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuo-Pin Chang , Hang-Ting Lue
CPC classification number: G11C16/0483 , G11C16/08 , H01L27/11582
Abstract: A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings. The memory device includes control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.
Abstract translation: 存储器件包括多个存储单元串。 导电条的多个堆叠包括构成为多个串中的串的第一串选择线的第一上条，被配置为用于多个字符串中的字符串的第二字符串选择行的第二上条和配置为字的中间条 用于多个字符串中的字符串的行。 存储器件包括耦合到第一串选择线和第二串选择线的控制电路，并且被配置为通过向第一串中的第一串选择线施加第一导通电压来选择多个串中的特定串 选择耦合到特定串的线，以及第二接通电压到耦合到特定串的第二串选择线中的第二串选择线。
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公开(公告)号：US20160314849A1
公开(公告)日：2016-10-27
申请号：US14692927
申请日：2015-04-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuo-Pin Chang
CPC classification number: G11C16/0483 , G11C7/18 , G11C16/0433 , G11C16/28 , G11C16/3427 , H01L27/11582
Abstract: A memory device includes: a plurality of conductive stacked structures including at least a string select line, a plurality of word lines and at least a ground select line; a plurality of memory cells formed in the conductive stacked structures; a plurality of bit lines, formed on the conductive stacked structures; and at least an odd common source line and at least an even common source line, formed on the conductive stacked structures. The odd common source line is coupled to a plurality of odd bit lines of the bit lines. The even common source line is coupled to a plurality of even bit lines of the bit lines.
Abstract translation: 存储器件包括：至少包括串选择线，多个字线和至少一地选线的多个导电堆叠结构; 形成在所述导电堆叠结构中的多个存储单元; 多个位线，形成在导电堆叠结构上; 以及形成在导电堆叠结构上的至少一个奇数公共源极线和至少一个偶数公共源极线。 奇数公共源极线耦合到位线的多个奇数位线。 偶数公共源极线耦合到位线的多个偶数位线。
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