公开(公告)号：US20160336339A1

公开(公告)日：2016-11-17

申请号：US14881350

申请日：2015-10-13

Applicant: Macronix International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L27/115 ,  G11C16/14 ,  H01L29/792 ,  H01L29/51 ,  H01L29/423 ,  G11C16/04 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C2216/02 ,  H01L27/11565 ,  H01L29/7926

Abstract: Embodiments of the present invention provide improved 3D non-volatile memory devices and associated methods. In one embodiment, a string of 3D non-volatile memory cells is provided. The string comprises a core extending along an axis of the string, the core having an elliptical cross section in a plane perpendicular to the axis; and a plurality of word lines, each word line disposed around a part of the core, the plurality of word lines spaced along the axis, and each word line corresponding to one of the memory cells. In various embodiments, at least one operating parameter is defined in order to improve the operation of the 3D non-volatile memory device.

Abstract translation: 本发明的实施例提供改进的3D非易失性存储器件和相关联的方法。 在一个实施例中，提供一串3D非易失性存储单元。 弦线包括沿着弦的轴线延伸的芯，芯在垂直于轴线的平面中具有椭圆形横截面; 以及多个字线，每个字线围绕所述芯的一部分设置，所述多个字线沿着所述轴间隔开，并且每个字线对应于所述存储器单元之一。 在各种实施例中，为了改善3D非易失性存储器件的操作，定义了至少一个操作参数。

公开(公告)号：US10340017B2

公开(公告)日：2019-07-02

申请号：US15803986

申请日：2017-11-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C8/14

Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

公开(公告)号：US09524784B1

公开(公告)日：2016-12-20

申请号：US14848524

申请日：2015-09-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11578 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582

Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.

Abstract translation: 本发明提供了用于控制对应于在非易失性存储器件的单元上执行功能的电压阈值分布的方法和相关联的器件。 在一个实施例中，提供了一种方法。 该方法可以包括提供非易失性存储器件。 该设备包括一个或多个字符串，每个字符串包括多个单元，多个单元包括第一单元和第二单元。 该方法还包括通过向第一单元施加第一功能电压和向第二单元施加第二功能电压来执行非易失性存储器件的功能。 第一功能电压和第二功能电压不同。

公开(公告)号：US09437319B1

公开(公告)日：2016-09-06

申请号：US14750065

申请日：2015-06-25

Applicant: Macronix International Co., Ltd.

Inventor： Atsuhiro Suzuki ,  Ya Jui Lee ,  Kuan Fu Chen ,  Chih-Wei Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459 ,  G11C16/3481 ,  G11C16/3486

Abstract: Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.

Abstract translation: 提供了在编程非易失性存储器时减少位线干扰的方法，装置和/或类似装置。 一种方法包括提供包括一组单元的非易失性存储器件，每个单元与位线相关联; 拍摄每个单元格上的编程电压; 检测每个单元的阈值电压; 至少部分地基于每个单元的检测到的阈值电压来识别该组单元的快速子集和该组单元的慢子集; 并拍摄编程电压，直到每个单元的阈值电压大于验证电压。 对于每个镜头，快速位线偏置被施加到与快速子集的每个单元相关联的位线，并且慢位线偏置被施加到与慢子集的每个单元相关联的位线。