公开(公告)号：US10340017B2

公开(公告)日：2019-07-02

申请号：US15803986

申请日：2017-11-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C8/14

Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

公开(公告)号：US09524784B1

公开(公告)日：2016-12-20

申请号：US14848524

申请日：2015-09-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11578 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582

Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.

Abstract translation: 本发明提供了用于控制对应于在非易失性存储器件的单元上执行功能的电压阈值分布的方法和相关联的器件。 在一个实施例中，提供了一种方法。 该方法可以包括提供非易失性存储器件。 该设备包括一个或多个字符串，每个字符串包括多个单元，多个单元包括第一单元和第二单元。 该方法还包括通过向第一单元施加第一功能电压和向第二单元施加第二功能电压来执行非易失性存储器件的功能。 第一功能电压和第二功能电压不同。

公开(公告)号：US11062759B1

公开(公告)日：2021-07-13

申请号：US16837041

申请日：2020-04-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Cheng-Hsien Cheng ,  Atsuhiro Suzuki ,  Yu-Hung Huang ,  Sheng-Kai Chen ,  Wen-Jer Tsai

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/409 ,  G11C11/4076

Abstract: A memory device and a programming method thereof are provided. The memory device includes a memory array, a plurality of word lines and a voltage generator. During a programming procedure, one of the word lines is at a selected state and others of the word lines are at a deselected state. Some of the word lines, which are at the deselected state, are classified into a first group and a second group. The first group and the second group are respectively located at two sides of the word line, which is at the selected state. The voltage generator provides a programming voltage to the word line, which is at the select state, during a programming duration. The voltage generator provides a first two-stage voltage waveform to the word lines in the first group and provides a second two-stage voltage waveform to the word lines in the second group.

公开(公告)号：US20170025179A1

公开(公告)日：2017-01-26

申请号：US14808745

申请日：2015-07-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/24 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10

Abstract: Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled to a bit line and word lines, the word lines arranged orthogonally to the NAND strings and establishing the memory cells at cross-points between surfaces of the NAND strings and the word lines, and a first set of discharge transistors positioned at an edge of the 3D array, coupled to a corresponding bit line, and configured for BL discharge, and a second set of discharge transistors positioned such that a first portion of BL potential is discharged through the first set of discharge transistors and a second portion through the second set.

Abstract translation: 本文中设想的方法和装置用于减少非易失性存储器件的位线恢复时间。 在示例性实施例中，非易失性存储器件包括非易失性存储器单元的3D阵列，包括多个块，每个块包括多个NAND串，每个NAND串耦合到位线和字线， 与NAND串正交排列的字线和在NAND串和字线的表面之间的交叉点建立存储单元，以及位于3D阵列边缘的第一组放电晶体管，耦合到相应的位线 并且被配置为用于BL放电，以及第二组放电晶体管，其定位成使得BL电位的第一部分通过第一组放电晶体管放电，并且通过第二组放电第二部分。

公开(公告)号：US20140127894A1

公开(公告)日：2014-05-08

申请号：US14153897

申请日：2014-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Shaw-Hung Ku ,  Chi-Pei Lu ,  Chun-Lien Su

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract translation: 本发明提供了一种非易失性存储器的制造方法，包括在衬底上形成栅介质层; 在栅介质层上形成浮栅; 在浮栅上形成第一电荷阻挡层; 在所述第一电荷阻挡层上形成氮化物层; 在所述氮化物层上形成第二电荷阻挡层; 在所述第二电荷阻挡层上形成控制栅极; 并对氮化物层进行处理以获得更高的介电常数。

公开(公告)号：US10460797B2

公开(公告)日：2019-10-29

申请号：US15698812

申请日：2017-09-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Ta-Wei Lin ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Wen-Jer Tsai

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

公开(公告)号：US20170098478A1

公开(公告)日：2017-04-06

申请号：US14873486

申请日：2015-10-02

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Lee ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: G11C29/38 ,  G11C16/26 ,  G11C29/44 ,  G11C16/14

CPC classification number: G11C29/38 ,  G11C16/08 ,  G11C16/26 ,  G11C29/025 ,  G11C29/44 ,  G11C2029/1202

Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.

公开(公告)号：US09548121B2

公开(公告)日：2017-01-17

申请号：US14742944

申请日：2015-06-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Lee ,  Shaw-Hung Ku ,  Cheng-Hsien Cheng

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/115 ,  H01L21/768

CPC classification number: G11C16/0483 ,  G11C2216/02 ,  H01L21/76802 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.

Abstract translation: 本文中设想的方法和装置用于增强非易失性存储器件的效率。 在示例实施例中，非易失性存储器件包括基板和非易失性存储单元的3D阵列，3D阵列包括通过绝缘层彼此分离的多个导电层，多个导电层包括顶层，顶部 层包括n个字符串选择行（SSL）和一个或多个底层，顶层还包括n-1个切割，每个切割电隔离两个SSL，其中每个切割被切割到顶层的深度并且不延伸到 底层和与多个层正交布置的多个垂直通道，多个通道中的每一个包括一串存储器单元，多个串中的每一个耦合到位线，SSL和一个或多个字线。

公开(公告)号：US09437612B1

公开(公告)日：2016-09-06

申请号：US14832220

申请日：2015-08-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Lee ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L29/10 ,  H01L27/115 ,  H01L29/16 ,  H01L29/04 ,  H01L29/49 ,  H01L29/51 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/7889 ,  H01L29/7926

Abstract: A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.

Abstract translation: 三维存储器，其包括存储单元堆叠结构。 存储单元堆叠结构由多个存储单元阵列结构和绝缘层交替堆叠，并且每个存储单元阵列结构包括字线，有源层，复合层和源极/漏极。 字线，有源层和复合层沿Y方向延伸。 有源层设置在相邻字线之间。 复合层设置在相邻字线和相邻有源层之间，并且每个复合层从有源层依次包括第一介电层，电荷存储层和第二介质层。 源/排水口以相等的间隔设置在活性层中。 存储单元包括两个相邻的源/漏极，两个相邻源极/漏极之间的有源层，有源层上的第一介电层，电荷存储层和第二介电层以及字线。

公开(公告)号：US11201169B2

公开(公告)日：2021-12-14

申请号：US16835360

申请日：2020-03-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Hsiung Lee ,  Shaw-Hung Ku

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11568 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.