公开(公告)号：US11758724B2

公开(公告)日：2023-09-12

申请号：US17167221

申请日：2021-02-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory device includes a substrate, a laminated structure and a memory string. The laminated structure is disposed on the substrate. The laminated structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The memory string is accommodated in the laminated structure along the first direction. The memory string includes a memory layer and a channel layer, and the memory layer is disposed between the laminated structure and the channel layer. At least a portion of the memory layer and the insulating layers are overlapped along the first direction.

公开(公告)号：US09443955B2

公开(公告)日：2016-09-13

申请号：US14539768

申请日：2014-11-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.

Abstract translation: 提供一种半导体器件。 两个堆叠层设置在第一导电类型的衬底上。 每个堆叠层包括电介质层和导电层。 电介质层设置在基板上。 导电层设置在电介质层上。 第二导电类型的第一掺杂区具有第一掺杂剂并且被布置在堆叠层之间的衬底中。 在第一掺杂区域中设置预非晶化注入（PAI）区域。 第二导电类型的第二掺杂区域具有第二掺杂剂并且被布置在PAI区域中。 第一导电类型与第二导电类型不同。 第二掺杂剂的扩散速度比第一掺杂剂的扩散速度快，并且第二掺杂剂的热激活高于第一掺杂剂的扩散速率。

公开(公告)号：US09324789B1

公开(公告)日：2016-04-26

申请号：US14723094

申请日：2015-05-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: H01L29/788 ,  H01L29/06 ,  H01L27/115 ,  H01L21/764 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The memory device is provided to include a substrate, a plurality of stack structures, conductive pillars, charge storage layers, and third conductive layers. The stack structures are arranged along a first direction and extend along a second direction, wherein each stack structure includes a plurality of first conductive layers and a plurality of dielectric layers that are alternately stacked along a third direction. Each conductive pillar is located on the substrate between two adjacent stack structures. Each charge storage layer is disposed between the stack structures and the conductive pillars. Each third conductive layer extending along the first direction overlaps the stack structures in a plurality of overlapped regions and covers a portion of top parts of the stack structures and the conductive pillars. An air gap is formed along the third direction in each overlapped region where the stacked structures and the third conductive layers overlap.

Abstract translation: 存储器件被设置为包括衬底，多个堆叠结构，导电柱，电荷存储层和第三导电层。 堆叠结构沿着第一方向布置并且沿着第二方向延伸，其中每个堆叠结构包括多个第一导电层和沿着第三方向交替堆叠的多个电介质层。 每个导电柱位于两个相邻堆叠结构之间的衬底上。 每个电荷存储层设置在堆叠结构和导电柱之间。 沿着第一方向延伸的每个第三导电层在多个重叠区域中重叠堆叠结构并覆盖堆叠结构的顶部部分和导电柱。 在堆叠结构和第三导电层重叠的重叠区域中沿着第三方向形成气隙。

公开(公告)号：US20140159134A1

公开(公告)日：2014-06-12

申请号：US13707426

申请日：2012-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.

Abstract translation: 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括设置在衬底上的栅极结构，掺杂区域，电荷存储层和第一介电层。 栅极结构两侧的基板上有凹槽。 栅极结构包括设置在衬底上的栅极电介质层和设置在栅极介电层上的栅极。 在栅介电层和衬底之间存在界面。 掺杂区域围绕凹部设置在基板中。 电荷存储层设置在凹部中，并且每个电荷存储层的顶表面高于界面。 第一介电层设置在电荷存储层与基板之间，电荷存储层与栅极结构之间。

公开(公告)号：US11177000B2

公开(公告)日：2021-11-16

申请号：US16445362

申请日：2019-06-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  Chih-Chieh Cheng ,  I-Chen Yang

IPC: G11C16/10 ,  H01L27/1157 ,  G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34

Abstract: An operating method of a non-volatile memory includes: generating a first programming pulse with a first time period to a target memory cell in a memory array; reading and verifying whether a threshold voltage of the target memory cell reaches a target voltage level; and generating a second programming pulse with a second time period to the target memory cell when the threshold voltage of the target memory cell does not reach the target voltage level, wherein the second time period is longer than the first time period.

公开(公告)号：US11018154B2

公开(公告)日：2021-05-25

申请号：US16543688

申请日：2019-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Chang Lu ,  Wen-Jer Tsai ,  Guan-Wei Wu ,  Yao-Wen Chang

IPC: H01L27/11582 ,  H01L29/36 ,  H01L29/10 ,  H01L23/528 ,  H01L21/265 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

公开(公告)号：US10763273B2

公开(公告)日：2020-09-01

申请号：US16110897

申请日：2018-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11565 ,  G11C16/26

Abstract: A memory device comprises an array of two-transistor memory cells, two-transistor memory cells in the array including a vertical select transistor and a vertical data storage transistor. The array comprises a plurality of stacks of conductive lines, a stack of conductive lines including a select gate line and a word line adjacent the select gate line. The device comprises an array of vertical channel lines disposed through the conductive lines to a reference line, gate dielectric structures surrounding the vertical channel lines at channel regions of vertical select transistors in the array of vertical channel lines and the select gate lines, charge storage structures surrounding the vertical channel lines at channel regions of vertical data storage transistors in the array of vertical channel lines and the word lines, and bit lines coupled to the vertical channel lines via upper ends of the vertical channel lines.

公开(公告)号：US20200066741A1

公开(公告)日：2020-02-27

申请号：US16110897

申请日：2018-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14

Abstract: A memory device comprises an array of two-transistor memory cells, two-transistor memory cells in the array including a vertical select transistor and a vertical data storage transistor. The array comprises a plurality of stacks of conductive lines, a stack of conductive lines including a select gate line and a word line adjacent the select gate line. The device comprises an array of vertical channel lines disposed through the conductive lines to a reference line, gate dielectric structures surrounding the vertical channel lines at channel regions of vertical select transistors in the array of vertical channel lines and the select gate lines, charge storage structures surrounding the vertical channel lines at channel regions of vertical data storage transistors in the array of vertical channel lines and the word lines, and bit lines coupled to the vertical channel lines via upper ends of the vertical channel lines.

公开(公告)号：US20180137918A1

公开(公告)日：2018-05-17

申请号：US15350157

申请日：2016-11-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42392

Abstract: “A method for operating a memory array includes an all programming step, an erasing step and a selectively programming step. The all programming step is to program all of memory cells of a NAND string. The erasing step is to erase the all of the memory cells of the string after the all programming step. The selectively programming step is to program a portion of the all of memory cells of the NAND string after the erasing step. The NAND string includes a pillar channel layer, a pillar memory layer and control gates. The pillar memory layer is surrounded by the control gates separated from each other. The memory cells are defined at intersections of the pillar channel layer and the control gates.”

公开(公告)号：US20150023098A1

公开(公告)日：2015-01-22

申请号：US13943691

申请日：2013-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0475 ,  G11C16/3422

Abstract: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.

Abstract translation: 提供了多级存储器的操作方法。 将低于标准读取电压的第一读取电压施加到存储器的控制栅极的一侧的衬底中的掺杂区域，以便确定第一存储位置和第二存储位置是否都处于最低级 。