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公开(公告)号：US09652179B2
公开(公告)日：2017-05-16
申请号：US14811970
申请日：2015-07-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hung-Sheng Chang , Hsiang-Pang Li , Chun-Ta Lin , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G06F3/06
CPC classification number: G06F3/0673 , G06F3/0608 , G06F3/061 , G06F3/064 , G06F3/0641
Abstract: A memory system is provided. The memory system includes a memory controller and a first memory block. The first memory block is configured to store a first data from a top of the first memory block in a top-down fashion. The first memory block is configured to store a first metadata corresponding to the first data from a bottom of the first memory block in a bottom-up fashion. The first data forms a first data area. The first metadata forms a first metadata area. And a first continuous space is formed between a bottom of the first data area and a top of the first metadata area.
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公开(公告)号：US11934480B2
公开(公告)日：2024-03-19
申请号：US16508189
申请日：2019-07-10
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hang-Ting Lue , Hung-Sheng Chang , Yi-Ching Liu
Abstract: A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.
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公开(公告)号：US11526285B2
公开(公告)日：2022-12-13
申请号：US16564066
申请日：2019-09-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wei-Chen Wang , Hung-Sheng Chang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.
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14.发明授权公开(公告)号：US10671296B2
公开(公告)日：2020-06-02
申请号：US15672430
申请日：2017-08-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hung-Sheng Chang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.
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公开(公告)号：US20200057561A1
公开(公告)日：2020-02-20
申请号：US15999604
申请日：2018-08-20
Applicant: Macronix International Co., Ltd.
Inventor： Chun-Hung Lai , Hung-Sheng Chang
Abstract: A processor receives, from an input device, input data for processing. Upon determining that the input data corresponds to an artificial intelligence (AI) application, the processor generates an AI command for performing read or write operations for a memory device that is configured to store data for a plurality of applications including the AI application, the AI command characterized by an operational code and including information about one or more components of the AI application corresponding to the input data. The processor sends the AI command and the input data to a storage controller managing the memory device, wherein the read or write operations for the memory device are performed by the storage controller using the operational code and the information included in the AI command. The processor receives, from the storage controller, a result of the read or write operations performed on the memory device.
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Patent Agency Ranking
公开(公告)号：US20190073136A1
公开(公告)日：2019-03-07
申请号：US15696325
申请日：2017-09-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hung-Sheng Chang , Hsiang-Pang Li , Tse-Yuan Wang , Che-Wei Tsao , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G06F3/06
Abstract: A memory controlling method, a memory controlling circuit and a memory system are provided. A memory includes a plurality of memory chips. The memory controlling method includes the following steps: The memory chips are grouped into at least two partner groups by a grouping unit. A quantity of the memory chips in each of the partner groups is at least two. At least one of the memory chips in each of the partner groups is required to serve a reading request or a writing request by a processing unit.
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公开(公告)号：US09817588B2
公开(公告)日：2017-11-14
申请号：US14683630
申请日：2015-04-10
Applicant: Macronix International Co., Ltd.
Inventor： Yu-Ming Chang , Wei-Chieh Huang , Li-Chun Huang , Hung-Sheng Chang , Hsiang-Pang Li , Ting-Yu Liu , Chien-Hsin Liu , Nai-Ping Kuo
IPC: G06F3/06 , G06F12/0806
CPC classification number: G06F3/0619 , G06F3/061 , G06F3/0655 , G06F3/0679 , G06F11/00 , G06F11/14 , G06F12/0246 , G06F12/0806 , G06F2212/621
Abstract: A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.
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公开(公告)号：US09547586B2
公开(公告)日：2017-01-17
申请号：US13939948
申请日：2013-07-11
Applicant: Macronix International Co., Ltd.
Inventor： Hung-Sheng Chang , Cheng-Yuan Wang , Hsiang-Pang Li , Yuan-Hao Chang , Pi-Cheng Hsiu , Tei-Wei Kuo
CPC classification number: G06F12/0238 , G06F12/0246 , G06F12/109 , G06F2212/1032 , G06F2212/7204 , G06F2212/7211
Abstract: A method is provided for managing a file system including data objects. The data objects, indirect pointers and source pointers are stored in containers that have addresses and include addressable units of a memory. The objects are mapped to addresses for corresponding containers. The indirect pointer in a particular container points to the address of a container in which the corresponding object is stored. The source pointer in the particular container points to the address of the container to which the object in the particular container is mapped. An object in a first container is moved to a second container. The source pointer in the first container is used to find a third container to which the object is mapped. The indirect pointer in the third container is updated to point to the second container. The source pointer in the second container is updated to point to the third container.
Abstract translation: 提供了一种用于管理包括数据对象的文件系统的方法。 数据对象，间接指针和源指针存储在具有地址并包含存储器可寻址单元的容器中。 对象映射到相应容器的地址。 特定容器中的间接指针指向存储相应对象的容器的地址。 特定容器中的源指针指向特定容器中的对象映射到的容器的地址。 将第一容器中的物体移动到第二容器。 第一个容器中的源指针用于查找对象映射到的第三个容器。 第三个容器中的间接指针被更新为指向第二个容器。 第二个容器中的源指针被更新为指向第三个容器。
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公开(公告)号：US09513815B2
公开(公告)日：2016-12-06
申请号：US14523006
申请日：2014-10-24
Applicant: Macronix International Co., Ltd.
Inventor： Ping-Chun Chang , Yuan-Hao Chang , Hung-Sheng Chang , Tei-Wei Kuo , Hsiang-Pang Li
CPC classification number: G06F3/061 , G06F3/064 , G06F3/0644 , G06F3/0679 , G06F12/023 , G06F12/0238 , G06F12/0292 , G06F2212/1024 , G06F2212/202 , G06F2212/214 , G06F2212/7201
Abstract: A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications. The plurality of physical memory segments is allocated to corresponding logical addresses based on the plurality of classifications, and on usage statistics of the physical memory segments. A data structure is maintained recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments. The plurality of classifications includes a first classification and a second classification having different usage statistic requirements than the first classification. Logical addresses having the second classification can be redirected to physical segments allocated to logical addresses having the first classification, and the data structure can be updated to record redirected logical addresses. A free command can release a physical memory segment allocated for main memory use.
Abstract translation: 提供了一种用于管理包括多个物理存储器段的存储器件的方法。 逻辑存储器空间根据使用规范被分类为多个分类。 基于多个分类，以及物理存储器段的使用统计，将多个物理存储器段分配给相应的逻辑地址。 数据结构保持在逻辑存储器空间中的逻辑地址和物理存储器段的物理地址之间进行记录转换。 多个分类包括与第一分类不同的使用统计要求的第一分类和第二分类。 具有第二分类的逻辑地址可以被重定向到分配给具有第一分类的逻辑地址的物理段，并且可以更新数据结构以记录重定向的逻辑地址。 免费命令可以释放分配给主内存使用的物理内存段。
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公开(公告)号：US11550709B2
公开(公告)日：2023-01-10
申请号：US16655510
申请日：2019-10-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wei-Chen Wang , Hung-Sheng Chang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.
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