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    Methods for fabricating a metal-oxide-semiconductor device structure and metal-oxide-semiconductor device structures formed thereby
    13.
    发明申请
    Methods for fabricating a metal-oxide-semiconductor device structure and metal-oxide-semiconductor device structures formed thereby 有权
    制造金属氧化物半导体器件结构的方法和由此形成的金属氧化物半导体器件结构

    公开(公告)号：US20050242378A1

    公开(公告)日：2005-11-03

    申请号：US11175582

    申请日：2005-07-06

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/338 ,  H01L29/49 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

    CPC分类号： H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

    摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

    摘要翻译： 一种制造金属氧化物半导体器件结构的方法。 该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。 选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影 栅电极中的掺杂物种类的范围位于栅电极内。 结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。

    METHOD FOR FABRICATING OXYGEN-IMPLANTED SILICON ON INSULATION TYPE SEMICONDUCTOR AND SEMICONDUCTOR FORMED THEREFROM
    16.
    发明申请
    METHOD FOR FABRICATING OXYGEN-IMPLANTED SILICON ON INSULATION TYPE SEMICONDUCTOR AND SEMICONDUCTOR FORMED THEREFROM 失效
    在绝缘型半导体上制造氧化硅的方法及其形成的半导体

    公开(公告)号：US20060226480A1

    公开(公告)日：2006-10-12

    申请号：US10907565

    申请日：2005-04-06

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    IPC分类号： H01L27/12 ,  H01L21/76

    CPC分类号： H01L21/76267 ,  H01L21/76243 ,  H01L21/76281 ,  H01L21/76283

    摘要： The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.

    摘要翻译： 本发明一般涉及一种用于制造氧注入半导体的方法，更具体地说，涉及一种用于将氧注入的硅绝缘（“SOI”）型半导体通过切割区域制造成器件尺寸的片之前的方法 SOI氧化工艺。 制造SOI的工艺顺序被修改，使得可以减少注入剂量并且相对较长并且可以缩短或消除高温退火工艺步骤。 如果在氧注入之后将晶片结构发送到焊盘形成以及掩模和蚀刻，则可以实现这种简化。 在蚀刻之后，可以执行退火或氧化工艺步骤以产生SOI晶片。

    Shrinking Contact Apertures Through LPD Oxide
    18.
    发明申请
    Shrinking Contact Apertures Through LPD Oxide 失效
    通过LPD氧化物收缩接触孔

    公开(公告)号：US20070099416A1

    公开(公告)日：2007-05-03

    申请号：US11163786

    申请日：2005-10-31

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

    摘要： Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.

    摘要翻译： 通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。 通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。 通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。 缩小的硬掩模然后限定通过电介质的亚光刻孔。

    Method of forming FinFET gates without long etches
    20.
    发明申请
    Method of forming FinFET gates without long etches 有权
    在没有长时间刻蚀的情况下形成FinFET栅极的方法

    公开(公告)号：US20050202607A1

    公开(公告)日：2005-09-15

    申请号：US10798907

    申请日：2004-03-11

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Hofak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Hofak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831

    摘要： A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.

    摘要翻译： 用于形成用于FinFET的栅极的方法使用一系列选择性沉积的侧壁与其它牺牲层一起形成可以准确可靠地形成栅极的空腔。 该技术避免了长时间的定向蚀刻步骤，以形成使用常规技术有助于形成FinFET的困难的栅极的临界尺寸。 特别地，首先在硅片上沉积可以精确地生长侧壁的牺牲种子层。 一旦牺牲种子层被蚀刻掉，侧壁可以被另一个一次性层包围。 蚀刻侧壁将导致跨过翅片形成的空腔，然后栅极导体材料可以沉积在这些空腔内。 因此，通过避免沿翅片的整个高度的长方向蚀刻，可以精确地控制所得FinFET栅极的高度和厚度。