公开(公告)号：US20050242378A1

公开(公告)日：2005-11-03

申请号：US11175582

申请日：2005-07-06

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/338 ,  H01L29/49 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

摘要翻译： 一种制造金属氧化物半导体器件结构的方法。 该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。 选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影 栅电极中的掺杂物种类的范围位于栅电极内。 结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。

公开(公告)号：US20050179029A1

公开(公告)日：2005-08-18

申请号：US10777576

申请日：2004-02-12

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： G11C13/02 ,  H01L21/336 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

摘要翻译： 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20050167655A1

公开(公告)日：2005-08-04

申请号：US10767065

申请日：2004-01-29

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： B82B1/00 ,  B82B3/00 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/70 ,  Y10S977/734 ,  Y10S977/742

摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

摘要翻译： 结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。 每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。 可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。 可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

公开(公告)号：US20050202322A1

公开(公告)日：2005-09-15

申请号：US10798908

申请日：2004-03-11

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F9/00

CPC分类号： G03F1/30

摘要： Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

摘要翻译： 用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。 所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。 图案层从手柄晶片转移到掩模板。 相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。 特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。

公开(公告)号：US20050106472A1

公开(公告)日：2005-05-19

申请号：US10707009

申请日：2003-11-13

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger, III ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger, III ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C23F3/00 ,  G03C5/00 ,  G03F1/00 ,  G03F9/00

CPC分类号： G03F1/30 ,  G03F1/54 ,  G03F1/68

摘要： The invention provides a method of forming a phase shift mask and the resulting phase shift mask. The method forms a non-transparent film on a transparent substrate and patterns an etch stop layer on the non-transparent film. The invention patterns the non-transparent film using the etch stop layer to expose areas of the transparent substrate. Next, the invention forms a mask on the non-transparent film to protect selected areas of the transparent substrate and forms a phase shift oxide on exposed areas of the transparent substrate. Subsequently, the mask is removed and the phase shift oxide is polished down to the etch stop layer, after which the etch stop layer is removed.

摘要翻译： 本发明提供一种形成相移掩模的方法和所得到的相移掩模。 该方法在透明基板上形成不透明的薄膜，并在非透明薄膜上形成蚀刻停止层。 本发明使用蚀刻停止层来图案化非透明膜以暴露透明基底的区域。 接下来，本发明在非透明膜上形成掩模，以保护透明基板的选定区域，并在透明基板的曝光区域上形成相移氧化物。 随后，去除掩模并将相移氧化物抛光到蚀刻停止层，之后去除蚀刻停止层。

公开(公告)号：US20050098804A1

公开(公告)日：2005-05-12

申请号：US10703355

申请日：2003-11-07

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/338 ,  H01L29/49 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

公开(公告)号：US20060166432A1

公开(公告)日：2006-07-27

申请号：US10905881

申请日：2005-01-25

申请人： Steven Holmes ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Larry Nesbit

发明人： Steven Holmes ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC分类号： H01L21/8242

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/3165 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

摘要： A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed to an oxide deposition bath, thereby causing deposition of oxide on those surfaces. Deposition of oxide on the top surface causes growth of the cap layer in a vertical direction and deposition of oxide on the side surface causes growth of the cap layer in a horizontal direction, thereby forming the beanie structure.

摘要翻译： 一种用于形成具有氧化物结构的氧化物半导体器件的方法（在器件的下面突出的氧化物盖）。 首先设置覆盖该部分的氧化物层，该层具有顶表面和侧表面。 然后将顶表面和侧表面暴露于氧化物沉积浴中，从而在这些表面上沉积氧化物。 顶部表面上的氧化物的沉积导致盖层在垂直方向上的生长，并且在侧面上的氧化物的沉积导致盖层在水平方向上的生长，从而形成豆瓣结构。

公开(公告)号：US20060226480A1

公开(公告)日：2006-10-12

申请号：US10907565

申请日：2005-04-06

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC分类号： H01L27/12 ,  H01L21/76

CPC分类号： H01L21/76267 ,  H01L21/76243 ,  H01L21/76281 ,  H01L21/76283

摘要： The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.

摘要翻译： 本发明一般涉及一种用于制造氧注入半导体的方法，更具体地说，涉及一种用于将氧注入的硅绝缘（“SOI”）型半导体通过切割区域制造成器件尺寸的片之前的方法 SOI氧化工艺。 制造SOI的工艺顺序被修改，使得可以减少注入剂量并且相对较长并且可以缩短或消除高温退火工艺步骤。 如果在氧注入之后将晶片结构发送到焊盘形成以及掩模和蚀刻，则可以实现这种简化。 在蚀刻之后，可以执行退火或氧化工艺步骤以产生SOI晶片。

公开(公告)号：US20060172496A1

公开(公告)日：2006-08-03

申请号：US10905979

申请日：2005-01-28

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/78654

摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

摘要翻译： 一种用于形成具有相互对准的双栅极的晶体管的方法。 该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中 栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。

公开(公告)号：US20050130341A1

公开(公告)日：2005-06-16

申请号：US10732951

申请日：2003-12-11

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： B82B3/00 ,  C01B31/02 ,  C30B25/02 ,  C30B29/02 ,  C30B29/60 ,  H01L29/15 ,  H01L29/786 ,  H01L51/30 ,  H01L21/336

CPC分类号： H01L51/0512 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/22 ,  C01B2202/34 ,  C30B25/02 ,  C30B29/02 ,  C30B29/605 ,  H01L51/0048 ,  Y10S977/854

摘要： Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.

摘要翻译： 从由衬底承载的多个合成位点上合成的导电和半导体碳纳米管的随机集合以及由此形成的结构选择半导体碳纳米管的方法。 在初始生长阶段之后，改变承载导电碳纳米管的合成位点，以在这些特定合成位点停止合成​​，从而停止导电碳纳米管的延长。 具有半导体碳纳米管的合成位点不受改变的影响，使得半导体碳纳米管可以被延长到比导电碳纳米管更长的长度。