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    DUAL WORK FUNCTION GATE ELECTRODES USING DOPED POLYSILICON AND A METAL SILICON GERMANIUM COMPOUND
    12.
    发明申请
    DUAL WORK FUNCTION GATE ELECTRODES USING DOPED POLYSILICON AND A METAL SILICON GERMANIUM COMPOUND 有权
    使用掺杂多晶硅和金属硅锗化合物的双功能门电极

    公开(公告)号：US20060292790A1

    公开(公告)日：2006-12-28

    申请号：US11463128

    申请日：2006-08-08

    申请人： Antonio Rotondaro ,  Mark Visokay ,  Luigi Colombo

    发明人： Antonio Rotondaro ,  Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L21/8242 ,  H01L29/76

    CPC分类号： H01L21/28097 ,  H01L21/823842 ,  H01L29/4975

    摘要： A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.

    摘要翻译： 在包含第一区域（20）和第二区域（30）的半导体（10）上形成介电层（50）。 在电介质层（50）上并在第一区域（20）和第二区域（30）之上形成多晶硅层。 多晶硅层可以包含0至50原子％的锗。 在多晶硅层和其中一个区域上形成金属层，并与下面的多晶硅层反应形成金属硅化物或金属锗化硅。 蚀刻多晶硅和金属硅化物或锗硅化物区域以分别形成晶体管栅极区域（60）和（90）。 如果需要，可以在金属栅极结构上方形成包覆层（100）。

    Method of fabricating a dielectric layer for a semiconductor structure
    17.
    发明申请
    Method of fabricating a dielectric layer for a semiconductor structure 审中-公开
    制造半导体结构的电介质层的方法

    公开(公告)号：US20050130438A1

    公开(公告)日：2005-06-16

    申请号：US10736444

    申请日：2003-12-15

    申请人： Antonio Rotondaro ,  Luigi Colombo

    发明人： Antonio Rotondaro ,  Luigi Colombo

    IPC分类号： H01L21/3115 ,  H01L21/314 ,  H01L21/318 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/823864 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/3185

    摘要： Fabricating a semiconductor structure includes establishing a non-stoichiometry associated with a dielectric layer, where the degree of non-stoichiometry corresponds to a nitrogen profile of the dielectric layer. Deposition of the dielectric layer outwardly from a substrate is controlled to substantially yield the established non-stoichiometry of the dielectric layer. Nitrogen is incorporated into the dielectric layer to substantially yield the nitrogen profile without nitridation of the interface.

    摘要翻译： 制造半导体结构包括建立与电介质层相关的非化学计量，其中非化学计量的程度对应于电介质层的氮分布。 电介质层从衬底向外沉积被控制以基本上产生介电层的已建立的非化学计量。 将氮气结合到电介质层中以基本上产生氮分布，而不会使界面氮化。

    Semiconductor CMOS Devices and Methods with NMOS High-K Dielectric Present in Core Region that Mitigate Damage to Dielectric Materials
    18.
    发明申请
    Semiconductor CMOS Devices and Methods with NMOS High-K Dielectric Present in Core Region that Mitigate Damage to Dielectric Materials 有权
    半导体CMOS器件和方法与NMOS High-K介质存在于核心区域，减轻对介质材料的损害

    公开(公告)号：US20070122962A1

    公开(公告)日：2007-05-31

    申请号：US11620447

    申请日：2007-01-05

    申请人： James Chambers ,  Mark Visokay ,  Luigi Colombo

    发明人： James Chambers ,  Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

    摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

    Process for manufacturing dual work function metal gates in a microelectronics device
    19.
    发明申请
    Process for manufacturing dual work function metal gates in a microelectronics device 有权

    公开(公告)号：US20070037343A1

    公开(公告)日：2007-02-15

    申请号：US11200741

    申请日：2005-08-10

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L29/66545

    摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

    Semiconductor structure and method of fabrication
    20.
    发明申请
    Semiconductor structure and method of fabrication 有权
    半导体结构及其制造方法

    公开(公告)号：US20050101145A1

    公开(公告)日：2005-05-12

    申请号：US10703388

    申请日：2003-11-06

    申请人： Mark Visokay ,  Luigi Colombo

    发明人： Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/8238

    CPC分类号： H01L21/823842

    摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.

    摘要翻译： 制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。 将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。 掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。 多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。 蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。