公开(公告)号：US20140231827A1

公开(公告)日：2014-08-21

申请号：US14141174

申请日：2013-12-26

申请人： Yukihiko WATANABE ,  Sachiko AOI ,  Masahiro SUGIMOTO ,  Akitaka SOENO ,  Shinichiro MIYAHARA

发明人： Yukihiko WATANABE ,  Sachiko AOI ,  Masahiro SUGIMOTO ,  Akitaka SOENO ,  Shinichiro MIYAHARA

IPC分类号： H01L29/47 ,  H01L29/45 ,  H01L29/16 ,  H01L21/285 ,  H01L29/78

CPC分类号： H01L29/47 ,  H01L21/0485 ,  H01L21/28518 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7813

摘要： A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

摘要翻译： 一种制造半导体器件的方法包括：在碳化硅层的一个主表面上的第一区域中形成欧姆电极，将欧姆电极硅化，并在第二区域中形成肖特基电极 具有自对准的碳化硅层。 在没有形成欧姆电极的情况下暴露第二区域。

公开(公告)号：US20080105903A1

公开(公告)日：2008-05-08

申请号：US11976450

申请日：2007-10-24

申请人： Masahito KODAMA ,  Eiko HAYSASHI ,  Masahiro SUGIMOTO

发明人： Masahito KODAMA ,  Eiko HAYSASHI ,  Masahiro SUGIMOTO

IPC分类号： H01L29/205 ,  H01L29/20 ,  H01L21/20

CPC分类号： H01L21/02433 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

摘要： The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects. A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B) Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.

摘要翻译： 本发明提供一种具有减少晶体缺陷数的III族氮化物基半导体的制造方法。 在具有C面作为主平面的蓝宝石衬底1上外延生长GaN层2（图1A）。 然后，通过在85℃下使用25％TMAH水溶液湿法蚀刻该层1小时，从而形成蚀刻坑4（图1B）然后，在GaN上生长GaN层5 层2通过ELO方法（图1C）。 如此形成的GaN层5的螺旋位错密度低于GaN层2的位错密度。

公开(公告)号：US20130330749A1

公开(公告)日：2013-12-12

申请号：US13968292

申请日：2013-08-15

申请人： Masahiro SUGIMOTO ,  Tomoyoshi SOGA

发明人： Tomoyoshi SOGA ,  Masahiro SUGIMOTO ,  Makoto SUEMATSU ,  Masashi HONMA ,  Takehito YAMAMOTO ,  Hiroshi SUZUKI

IPC分类号： G01N33/487 ,  G01N33/497

CPC分类号： G01N33/487 ,  C07K5/0215 ,  G01N33/497 ,  G01N33/576 ,  G01N33/6812 ,  G01N33/6893 ,  G01N2800/08 ,  G01N2800/60

摘要： A normal person (i.e. a control) and liver diseases such as drug induced liver injury, an asymptomatic hepatitis B carrier, an asymptomatic hepatitis C carrier, chronic hepatitis B, chronic hepatitis C, liver cancer, a nonalcoholic fatty liver disease (NAFLD), nonalcoholic steatohepatitis (NASH), and simple steatosis (SS) are identified by measuring the concentrations of γ-Glu-X (X represents an amino acid or an amine) peptides or the levels of AST or ALT in blood and carrying out, for example, a multiple logistic regression based on the measured value.

摘要翻译： 正常人（即对照）和肝脏疾病如药物诱发的肝损伤，无症状乙型肝炎携带者，无症状丙型肝炎携带者，慢性乙型肝炎，慢性丙型肝炎，肝癌，非酒精性脂肪性肝病（NAFLD） 通过测量血液中的γ-Glu-X（X代表氨基酸或胺）肽的浓度或AST或ALT的水平，进行例如，通过测定非酒精性脂肪性肝炎（NASH）和简单脂肪变性（SS） ，基于测量值的多重逻辑回归。

公开(公告)号：US20140319577A1

公开(公告)日：2014-10-30

申请号：US14244038

申请日：2014-04-03

申请人： Masahiro SUGIMOTO ,  Yuichi Takeuchi

发明人： Masahiro SUGIMOTO ,  Yuichi Takeuchi

IPC分类号： H01L29/739 ,  H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7789

摘要： A semiconductor device disclosed in this specification includes a p+ contact region, an n+ source region, a p− base region, an n− drift region, a gate electrode, an insulator, a p+ electric field alleviating layer, and a p− positive hole extraction region. The electric field alleviating layer has same impurity concentration as the base region or higher, contacts a lower surface of the base region, and is formed in a same depth as the gate trench or in a position deeper than the gate trench. A positive hole extraction region extends to contact the electric field alleviating layer from a position to contact an upper surface of a semiconductor substrate or a first semiconductor region, and extracts a positive hole that is produced in the electric field alleviating layer at the avalanche breakdown to the upper surface of the semiconductor substrate.

摘要翻译： 在本说明书中公开的半导体装置包括p +接触区域，n +源极区域，基极区域，n漂移区域，栅电极，绝缘体，p +电场缓和层和ap-空穴提取区域 。 电场缓和层具有与基底区域相同的杂质浓度或更高的接触基底区域的下表面，并且形成在与栅极沟槽相同的深度或比栅极沟槽更深的位置。 正空穴提取区域延伸以从与半导体衬底或第一半导体区域的上表面接触的位置接触电场缓和层，并且在雪崩击穿时提取在电场减轻层中产生的正空穴 半导体衬底的上表面。

公开(公告)号：US20140319540A1

公开(公告)日：2014-10-30

申请号：US14258251

申请日：2014-04-22

申请人： Masahiro SUGIMOTO

发明人： Masahiro SUGIMOTO

IPC分类号： H01L27/16

CPC分类号： H01L29/0653 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7804

摘要： A semiconductor device is provided with a semiconductor substrate in which a power semiconductor element part and a temperature sensing diode part are provided. The temperature sensing diode part includes a first semiconductor region, a second semiconductor region, a first base region, and a first drift region. In the semiconductor substrate, an isolation trench is formed, which passes through the first base region, extends to the first drift region, and surrounds an outer periphery of the temperature sensing diode part. At least a part of one of side walls of the isolation trench is in contact with the power semiconductor element part, and the other side wall of the isolation trench is in contact with the temperature sensing diode part.

摘要翻译： 半导体器件设置有半导体衬底，其中提供功率半导体元件部分和温度感测二极管部分。 温度感测二极管部分包括第一半导体区域，第二半导体区域，第一基极区域和第一漂移区域。 在半导体衬底中，形成隔离沟槽，其通过第一基极区域延伸到第一漂移区域并且包围温度感测二极管部件的外周。 隔离沟槽的一个侧壁的至少一部分与功率半导体元件部分接触，并且隔离沟槽的另一个侧壁与温度感测二极管部分接触。

公开(公告)号：US20080105954A1

公开(公告)日：2008-05-08

申请号：US11976451

申请日：2007-10-24

申请人： Masahito KODAMA ,  Eiko HAYASHI ,  Masahiro SUGIMOTO

发明人： Masahito KODAMA ,  Eiko HAYASHI ,  Masahiro SUGIMOTO

IPC分类号： H01L29/06 ,  H01L21/306

CPC分类号： H01L29/7813 ,  H01L21/32134 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/432 ,  H01L29/66734 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8613 ,  H01L33/24 ,  H01L33/382 ,  H01S5/0421 ,  H01S5/32341

摘要： A group III nitride based semiconductor device which has a trench or mesa structure and of which leakage of current and reduction of breakdown voltage are prevented. A GaN layer 2 was grown on a C-plane sapphire substrate 1, and a T-shaped USG film 3 was formed on the GaN layer 2 so that side surfaces of the USG film 3 were arranged parallel to A-plane and M-plane of the GaN layer 2. Thereafter, by using the USG film 3 as a mask, the GaN layer 2 was dry-etched. As is clear from FIGS. 2A and 2B, the M-plane is less roughened as compared with the A-plane. Subsequently, wet-etched was performed by use of an aqueous TMAH solution. As is clear from FIGS. 2C and 2D, roughness of the A-plane and the M-plane are removed, and, particularly, the M-plane assumes a mirror surface. Thus, through provision of M-plane side surfaces of a trench or an etching-formed mesa, leakage of current and reduction of breakdown voltage of a group III nitride based semiconductor device can be prevented.

摘要翻译： 具有沟槽或台面结构，并且防止电流泄漏和击穿电压降低的III族氮化物基半导体器件。 在C面蓝宝石衬底1上生长GaN层2，在GaN层2上形成T形USG膜3，使得USG膜3的侧面平行于A面和M面 的GaN层2。 此后，通过使用USG膜3作为掩模，对GaN层2进行干式蚀刻。 从图 如图2A和2B所示，与A平面相比，M平面不那么粗糙。 随后，使用TMAH水溶液进行湿蚀刻。 从图 如图2C和2D所示，去除了A平面和M面的粗糙度，特别地，M平面呈现镜面。 因此，通过设置沟槽的M面侧面或蚀刻形成的台面，可以防止III族氮化物类半导体器件的漏电流和击穿电压的降低。