公开(公告)号：US08115545B2

公开(公告)日：2012-02-14

申请号：US13177958

申请日：2011-07-07

Applicant: Chiang Pu ,  Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien-Chun Yang

Inventor： Chiang Pu ,  Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien-Chun Yang

IPC: H03F1/36

CPC classification number: G01C19/5776

Abstract: Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.

Abstract translation: 一些实施例涉及一种电路，包括：提供电阻的高压晶体管; 放大器，被配置为接收电流并将电流转换成在产生电流的环路中使用的第一电压; 以及自动电平控制电路，其基于所述第一电压的交流振幅调整所述高电压晶体管的栅极处的第二电压，从而调整所述电阻和所述第一电压; 其中所述自动电平控制电路被配置为如果所述第一电压与第一参考电压不同，则将所述第一电压调整为朝向所述第一参考电压。

公开(公告)号：US20110199152A1

公开(公告)日：2011-08-18

申请号：US12706886

申请日：2010-02-17

Applicant: Steven SWEI ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

Inventor： Steven SWEI ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

IPC: G05F1/10

CPC classification number: G05F1/10 ,  G05F3/02 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898

Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

Abstract translation: 集成电路包括第一电流源。 第二电流源经由导线与第一电流源电耦合。 开关电路耦合在第一电流源和第二电流源之间。 第一电路耦合在第一节点和第二节点之间。 第一节点设置在第一电流源和开关电路之间。 第二节点与第一电流源耦合。 第一电路被配置为基本上均衡第一节点和第二节点上的电压。 第二电路耦合在第三节点和第四节点之间。 第三节点设置在第二电流源和开关电路之间。 第四节点被布置成与第二电流源耦合。 第二电路被配置为基本上均衡第三节点和第四节点上的电压。

公开(公告)号：US5710450A

公开(公告)日：1998-01-20

申请号：US363749

申请日：1994-12-23

Applicant: Robert S. Chau ,  Chan-Hong Chern ,  Chia-Hong Jan ,  Kevin R. Weldon ,  Paul A. Packan ,  Leopoldo D. Yau

Inventor： Robert S. Chau ,  Chan-Hong Chern ,  Chia-Hong Jan ,  Kevin R. Weldon ,  Paul A. Packan ,  Leopoldo D. Yau

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66613 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Abstract translation: 具有低电阻超浅尖端区域的新型晶体管及其制造方法。 本发明的新型晶体管具有源/漏扩展或尖端区域，其包括在栅电极下方延伸的超浅区域和升高区域。

公开(公告)号：US09489989B2

公开(公告)日：2016-11-08

申请号：US12820712

申请日：2010-06-22

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien Chun Yang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien Chun Yang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: G11C11/22 ,  G11C11/24 ,  G11C7/06 ,  G11C5/14 ,  G11C8/00

CPC classification number: G11C11/4074 ,  G11C5/147

Abstract: A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.

Abstract translation: 电压调节器包括与电压调节器的输出端电耦合的输出级。 输出级包括具有体积和漏极的至少一个晶体管。 至少一个背偏置电路与所述至少一个晶体管的主体电耦合。 至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

公开(公告)号：US08854104B2

公开(公告)日：2014-10-07

申请号：US13793681

申请日：2013-03-11

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Tsung-Ching (Jim) Huang ,  Chih-Chang Lin ,  Ming-Chieh Huang

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Tsung-Ching (Jim) Huang ,  Chih-Chang Lin ,  Ming-Chieh Huang

IPC: H03L5/00

CPC classification number: H03L5/00 ,  H03K3/356182 ,  H03K17/102 ,  H03K19/018521

Abstract: A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch.

Abstract translation: 电路包括第一电容性装置和第一锁存器。 第一电容性装置包括被配置为接收第一输入信号的第一端和与第一锁存器耦合的第二端。 第一锁存器包括第一类型的第一晶体管和第二晶体管。 第一晶体管的第一端子和第二晶体管的第一端子都被配置为接收第一电压值。 第一晶体管的第二端与第二晶体管的第三端耦合。 第一晶体管的第三端子与第二晶体管的第二端子和电容器件的第二端耦合，并且被配置为提供用于第一锁存器的输出电压。

公开(公告)号：US08766613B2

公开(公告)日：2014-07-01

申请号：US13744037

申请日：2013-01-17

Applicant: Chan-Hong Chern ,  Tzu-Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

Inventor： Chan-Hong Chern ,  Tzu-Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

IPC: G05F1/44

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.

Abstract translation: 一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。 控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。 通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。 响应于输出节点处的电压电平产生反馈信号。 耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

公开(公告)号：US08625240B2

公开(公告)日：2014-01-07

申请号：US13293853

申请日：2011-11-10

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H02H3/22

CPC classification number: H02H9/04 ,  H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H03F2200/294 ,  H03F2203/45638 ,  H03G1/0023 ,  H03K3/35613 ,  H03K19/018514 ,  H01L2924/00

Abstract: An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.

Abstract translation: 输入/输出（I / O）电路包括与I / O电路的输出节点电耦合的静电放电（ESD）保护电路。 至少一个电感器和至少一个负载以串联方式电耦合，并且在I / O电路的输出节点和电力线之间。 电路与所述至少一个电感器和所述至少一个负载之间的节点电耦合。 电路可操作以在信号转换期间增加流过至少一个电感器的电流。

公开(公告)号：US08588358B2

公开(公告)日：2013-11-19

申请号：US13045788

申请日：2011-03-11

Applicant: Chan-Hong Chern ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Fu-Lung Hsueh

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/113 ,  H04L7/0337

Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.

Abstract translation: 时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。 延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。 电荷泵配置为控制LCVCO。 相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。

公开(公告)号：US08493124B2

公开(公告)日：2013-07-23

申请号：US12843479

申请日：2010-07-26

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Chih-Chang Lin

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

Abstract translation: 电平移位器包括一个PMOS和两个NMOS晶体管。 第一NMOS晶体管的源极耦合到低电源电压。 输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。 输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。 输出信号耦合在PMOS和第一NMOS晶体管之间。 第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1， 输入信号为逻辑0。

公开(公告)号：US08436671B2

公开(公告)日：2013-05-07

申请号：US12859456

申请日：2010-08-19

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

IPC: H03L5/00

CPC classification number: H03K3/02 ,  H03K19/018521 ,  H03K19/018528

Abstract: A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.

Abstract translation: 电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。 电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。 高电源电压高于第一电压电平。 所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。 第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。