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    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR
    12.
    发明申请
    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR 有权
    带有收集器的自对准双极晶体管的结构和方法

    公开(公告)号：US20050184359A1

    公开(公告)日：2005-08-25

    申请号：US10708340

    申请日：2004-02-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/737

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

    摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

    Field-shield-trench isolation for gigabit DRAMs
    14.
    发明授权
    Field-shield-trench isolation for gigabit DRAMs 有权
    用于千兆位DRAM的场屏蔽沟槽隔离

    公开(公告)号：US06762447B1

    公开(公告)日：2004-07-13

    申请号：US09245269

    申请日：1999-02-05

    申请人： Jack A. Mandelman ,  Rama Divakaruni ,  Giuseppe Larosa ,  Ulrike Gruening ,  Carl Radens

    发明人： Jack A. Mandelman ,  Rama Divakaruni ,  Giuseppe Larosa ,  Ulrike Gruening ,  Carl Radens

    IPC分类号： H01L27108

    CPC分类号： H01L27/10861 ,  H01L21/763 ,  H01L21/765 ,  H01L27/10829 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.

    摘要翻译： 形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。 隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。 这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。 隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于 与半导体本体电接触。 隔离沟槽的上部填充有第二电绝缘体。

    High performance FET with elevated source/drain region
    15.
    发明授权
    High performance FET with elevated source/drain region 失效
    具有升高的源极/漏极区域的高性能FET

    公开(公告)号：US07566599B2

    公开(公告)日：2009-07-28

    申请号：US10996866

    申请日：2004-11-24

    申请人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

    发明人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

    IPC分类号： H01L21/00

    CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

    摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

    摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

    INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES
    16.
    发明申请
    INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES 失效
    多金属门工作功能结构的整合方案

    公开(公告)号：US20090108356A1

    公开(公告)日：2009-04-30

    申请号：US11924053

    申请日：2007-10-25

    申请人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

    发明人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

    IPC分类号： H01L29/78 ,  H01L21/44

    CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

    摘要翻译： 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。