公开(公告)号：US10108372B2

公开(公告)日：2018-10-23

申请号：US14605593

申请日：2015-01-26

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

公开(公告)号：US09213603B2

公开(公告)日：2015-12-15

申请号：US14456559

申请日：2014-08-11

Applicant: Micron Technology, Inc.

Inventor： Federico Tiziani ,  Giovanni Campardo ,  Massimo Iaculo ,  Claudio Giaccio ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Ornella Vitale ,  Antonino Pollio

IPC: G11C29/00 ,  G06F11/10 ,  G06F13/16 ,  G06F1/32 ,  G06F12/02

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F13/1668 ,  G11C29/52 ,  Y02D10/14

Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.

Abstract translation: 在各种实施例中，单个虚拟化纠错码（ECC）NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。 在各种实施例中，控制器管理多个NAND存储器件。 控制器一次为多个NAND存储器件中的一个选择一个供电，以节省存储系统的整体功耗。

公开(公告)号：US20240427699A1

公开(公告)日：2024-12-26

申请号：US18747037

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Mattia Robustelli ,  Innocenzo Tortorelli ,  Alessandro Novati ,  Nicola Colella ,  Antonino Pollio

IPC: G06F12/02 ,  G06F13/16

Abstract: The subject application related to referencing memory using portions of a split logical block address. A method includes receiving a memory operation including a logical block address (LBA). The method also includes splitting the LBA into a first portion and a second portion. The method further includes determining a physical block of a memory using a logical-to-physical (L2P) table to map the first portion of the LBA to the physical block. The physical block includes a plurality of physical block addresses (PBAs). The method further includes combining the second portion of the LBA and the physical block to reference a physical block address (PBA) of the physical block. The method further includes performing the memory operation at the PBA of the physical block.

公开(公告)号：US20240168889A1

公开(公告)日：2024-05-23

申请号：US18428758

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0873

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F12/0873

Abstract: A method includes: creating a logical-to-physical address translation (L2P) bitmap for each respective virtual block programmed across a plane of multiple dice of a memory device, each L2P bitmap identifying logical addresses, within each respective L2P table of a plurality of L2P tables, that belong to a respective virtual block; creating a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table, of the plurality of L2P tables, based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular virtual block; and identifying and updating, by the processing device, an L2P bitmap associated with the particular virtual block for an L2P mapping corresponding to the entry.

公开(公告)号：US11928063B1

公开(公告)日：2024-03-12

申请号：US17890507

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Gianfranco Ferrante

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F12/0873

Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.

公开(公告)号：US11886341B2

公开(公告)日：2024-01-30

申请号：US17850584

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Hua Tan

IPC: G06F12/00 ,  G06F12/0802 ,  G06F12/02

CPC classification number: G06F12/0802 ,  G06F12/0223 ,  G06F2212/604 ,  G06F2212/608

Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

公开(公告)号：US20230161696A1

公开(公告)日：2023-05-25

申请号：US18058132

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio

IPC: G06F12/02

CPC classification number: G06F12/0253 ,  G06F2212/7205 ,  G06F2212/702

Abstract: Methods, systems, and devices for data separation for garbage collection are described. A control component coupled to the memory array may identify a source block for a garbage collection procedure. In some cases, a first set of pages of the source block may be identified as a first type associated with a first access frequency and a second set of pages of the source block ay be identified as a second type associated with a second access frequency. Once the pages are identified as either the first type or the second type, the first set of pages may be transferred to a first destination block, and the second set of pages may be transferred to a second destination block as part of the garbage collection procedure.

公开(公告)号：US11023167B2

公开(公告)日：2021-06-01

申请号：US16136101

申请日：2018-09-19

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F12/00 ,  G06F3/06

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

公开(公告)号：US20190018618A1

公开(公告)日：2019-01-17

申请号：US16136101

申请日：2018-09-19

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

公开(公告)号：US20150212738A1

公开(公告)日：2015-07-30

申请号：US14605593

申请日：2015-01-26

Applicant: Micron Technology, Inc.

Inventor： GIUSEPPE D'ELISEO ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

Abstract translation: 公开了用于在存储器中执行多个排队任务的方法和装置。 一个示例性设备包括被配置为耦合到主机的存储器。 存储器还被配置为从主机接收多个存储器访问请求，状态请求和执行命令，并且响应于来自主机的执行命令来执行多个存储器访问请求中的一个或多个。 执行命令包括与多个存储器访问请求的每个相应存储器访问请求对应的多个相应指示，并且指示主机是否请求存储器执行每个相应的存储器访问请求。