公开(公告)号：US20200350021A1

公开(公告)日：2020-11-05

申请号：US16935740

申请日：2020-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: Memories having a controller configured to apply a particular multi-step programming pulse to a selected access line of a programming operation, enable for programming memory cells that have a particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a first threshold voltage level while applying a first step of a multi-step programming pulse to the selected access line, and enable for programming memory cells that have the particular desired data state for the programming operation and are deemed to have a threshold voltage lower than a second threshold voltage level and higher than the first threshold voltage level while applying a second step of the multi-step programming pulse, lower than the first step of the multi-step programming pulse, to the selected access line.

公开(公告)号：US10741252B2

公开(公告)日：2020-08-11

申请号：US16223305

申请日：2018-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a particular multi-step programming pulse to a selected access line of a programming operation, and applying a next subsequent multi-step programming pulse to the selected access line, wherein the particular multi-step programming pulse has a first step having a first voltage level and a second step having a second voltage level different than the first voltage level, and wherein the next subsequent multi-step programming pulse has a first step having a third voltage level and a second step having a fourth voltage level different than the third voltage level and higher than the first voltage level.

公开(公告)号：US20190295614A1

公开(公告)日：2019-09-26

申请号：US16429209

申请日：2019-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/18 ,  G11C8/04 ,  G11C7/10

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US10373970B2

公开(公告)日：2019-08-06

申请号：US15058921

申请日：2016-03-02

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee

IPC: H01L27/11573 ,  H01L27/11575 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11526 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

Abstract: A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. Additional semiconductor device structures, methods of faulting semiconductor device structures, and electronic systems are also described.

公开(公告)号：US12300332B2

公开(公告)日：2025-05-13

申请号：US18369479

申请日：2023-09-18

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/26 ,  G11C7/10 ,  G11C16/10 ,  G11C16/34

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US20240361929A1

公开(公告)日：2024-10-31

申请号：US18768806

申请日：2024-07-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.

公开(公告)号：US12131060B2

公开(公告)日：2024-10-29

申请号：US17872426

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Dung V. Nguyen ,  Dave Scott Ebsen ,  Tomoharu Tanaka ,  James Fitzpatrick ,  Huai-Yuan Tseng ,  Akira Goda ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

公开(公告)号：US12073891B2

公开(公告)日：2024-08-27

申请号：US17682089

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Violante Moschiano ,  Jeffrey S. McNeil ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C16/102 ,  G11C16/26 ,  G11C2207/2254

Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.

公开(公告)号：US20240177755A1

公开(公告)日：2024-05-30

申请号：US18388032

申请日：2023-11-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Eric N. Lee ,  Tomoko Ogura Iwasaki ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Kishore Kumar Muchherla

IPC: G11C11/00 ,  G06F12/02 ,  G11C16/04

CPC classification number: G11C11/005 ,  G06F12/0246 ,  G11C16/0483

Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells

公开(公告)号：US11977778B2

公开(公告)日：2024-05-07

申请号：US17691014

申请日：2022-03-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Jonathan S. Parry ,  Lakshmi Kalpana Vakati

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.