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    Write operation techniques for memory systems
    11.
    发明授权
    Write operation techniques for memory systems 有权

    公开(公告)号：US11244717B2

    公开(公告)日：2022-02-08

    申请号：US16700948

    申请日：2019-12-02

    Applicant: Micron Technology, Inc.

    Inventor： Zhongyuan Lu ,  Christina Papagianni ,  Hongmei Wang ,  Robert J. Gleixner

    IPC: G11C11/406 ,  G11C11/409 ,  G11C7/22 ,  G11C11/56 ,  G11C11/408

    Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.

    Polarity-conditioned memory cell write operations
    12.
    发明授权
    Polarity-conditioned memory cell write operations 有权

    公开(公告)号：US10748615B2

    公开(公告)日：2020-08-18

    申请号：US16419831

    申请日：2019-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Hongmei Wang ,  Luca Crespi ,  Debayan Mahalanabis ,  Fabio Pellizzer

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.

    POLARITY-CONDITIONED MEMORY CELL WRITE OPERATIONS
    13.
    发明申请
    POLARITY-CONDITIONED MEMORY CELL WRITE OPERATIONS 审中-公开

    公开(公告)号：US20190311768A1

    公开(公告)日：2019-10-10

    申请号：US16419831

    申请日：2019-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Hongmei Wang ,  Luca Crespi ,  Debayan Mahalanabis ,  Fabio Pellizzer

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.

    Polarity-conditioned memory cell write operations
    15.
    发明授权
    Polarity-conditioned memory cell write operations 有权

    公开(公告)号：US10354729B1

    公开(公告)日：2019-07-16

    申请号：US15857188

    申请日：2017-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Hongmei Wang ,  Luca Crespi ,  Debayan Mahalanabis ,  Fabio Pellizzer

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.

    Drift mitigation with embedded refresh
    18.
    发明授权
    Drift mitigation with embedded refresh 有权

    公开(公告)号：US10269442B1

    公开(公告)日：2019-04-23

    申请号：US15857125

    申请日：2017-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Hongmei Wang

    IPC: G11C29/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.

    Medical device data analysis
    19.
    发明授权
    Medical device data analysis 有权

    公开(公告)号：US12033753B2

    公开(公告)日：2024-07-09

    申请号：US16989749

    申请日：2020-08-10

    Applicant: Micron Technology, Inc.

    Inventor： Gitanjali T. Ghosh ,  Irene K. Thompson ,  Jessica M. Maderos ,  Hongmei Wang ,  Fatma Arzum Simsek-Ege ,  Kathryn H. Russo

    IPC: G16H40/67 ,  G16H10/60 ,  G16H40/63 ,  G16H80/00

    CPC classification number: G16H40/67 ,  G16H10/60 ,  G16H40/63 ,  G16H80/00

    Abstract: Systems, apparatuses, and methods related to medical device data analysis are described. In some examples, a medical device is implanted in a user of the medical device and the data generated by the medical device is not easily accessible to the user. In an example, a controller can be configured to receive, by a mobile device coupled to a medical device, data from the medical device, where the data is a part of a baseline dataset related to the medical device. The controller can be configured to receive different data from the medical device, where the different data is received from the medical device as the different data is generated by the medical device, analyze the data from the medical device and the different data generated by the medical device, and perform an action based on the analyzed data and the different data generated by the medical device.

    PROGRAMMABLE CHALCOGENIDE CAPACITORS
    20.
    发明公开
    PROGRAMMABLE CHALCOGENIDE CAPACITORS 审中-公开

    公开(公告)号：US20240055190A1

    公开(公告)日：2024-02-15

    申请号：US17884450

    申请日：2022-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Hongmei Wang ,  Huiqi Gong ,  Peng Zhao ,  Jingshan Wang ,  Giovanni Ferrari

    IPC: H01G7/06

    CPC classification number: H01G7/06

    Abstract: Methods, systems, and devices for programmable chalcogenide capacitors are described. A first programming pulse may be applied, for a first duration, to a capacitor comprising a chalcogenide material to adjust a capacitance of the capacitor from a first capacitance to a second capacitance. A pulse may be applied to the capacitor based on applying the first programming pulse to the capacitor. A first voltage may be stored in the capacitor based on adjusting the capacitance of the capacitor from the first capacitance to the second capacitance, and the first voltage may be stored based on the capacitor having the second capacitance.

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