公开(公告)号：US20220293506A1

公开(公告)日：2022-09-15

申请号：US17830022

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

公开(公告)号：US10381297B2

公开(公告)日：2019-08-13

申请号：US16027041

申请日：2018-07-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

公开(公告)号：US20190109080A1

公开(公告)日：2019-04-11

申请号：US16200843

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4825 ,  H01L21/76879 ,  H01L21/7688 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/10126 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/35121 ,  H01L2924/013 ,  H01L2924/00014

Abstract: An electronic device includes a substrate, a structure over the substrate having an edge wall defining at least a portion of an opening exposing a surface of the substrate, and a dielectric material adjacent and in contact with the edge wall and an adjacent portion of the surface of the substrate. The dielectric material has a profile tapering downward from adjacent the edge wall toward the substrate. Other electronic devices include a substrate and a solder mask over the substrate. The solder mask defines an opening therethrough. A supplemental mask is within the opening of the solder mask, and has a sidewall that slopes away from the solder mask. A conductive structure is adjacent and in contact with at least one of the solder mask or the supplemental mask.

公开(公告)号：US10032703B2

公开(公告)日：2018-07-24

申请号：US15229668

申请日：2016-08-05

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

公开(公告)号：US09418926B1

公开(公告)日：2016-08-16

申请号：US14714599

申请日：2015-05-18

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/492 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/14179 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

Abstract translation: 封装半导体器件的封装封装系统。 在一个实施例中，封装封装系统包括第一半导体封装器件和第二半导体封装器件。 第一包装装置包括：基材，具有包含芯片附着区域和周边区域的第一面，在芯片附着区域附着到基板的第一半导体管芯，其中，第一半导体管芯具有面向 基底基板的第一侧和与基底基板的第一侧间隔开第一距离的背面，以及在基板的周边区域中在芯片附着区域外侧的高密度互连阵列。 互连阵列具有从基底衬底的第一侧延伸大于第一距离的第二距离的多个互连。 第二半导体器件封装电耦合相应的单独互连。