公开(公告)号：US11087806B2

公开(公告)日：2021-08-10

申请号：US16000149

申请日：2018-06-05

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

公开(公告)号：US11049543B2

公开(公告)日：2021-06-29

申请号：US16559344

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Yasuo Satoh ,  Kenji Mae

IPC: G11C7/00 ,  G11C11/406 ,  H03L7/081

Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.

公开(公告)号：US10516391B2

公开(公告)日：2019-12-24

申请号：US15839531

申请日：2017-12-12

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Kazutaka Miyano

IPC: H03K3/017 ,  H03K5/156 ,  G11C7/22 ,  H03L7/081 ,  G11C7/12 ,  G11C11/4076 ,  G11C7/10

Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.

公开(公告)号：US20180358064A1

公开(公告)日：2018-12-13

申请号：US16107909

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C8/18 ,  G11C7/10 ,  G11C29/02 ,  G11C11/4076

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US20180286470A1

公开(公告)日：2018-10-04

申请号：US16000149

申请日：2018-06-05

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

公开(公告)号：US20180053538A1

公开(公告)日：2018-02-22

申请号：US15243651

申请日：2016-08-22

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

公开(公告)号：US20170309323A1

公开(公告)日：2017-10-26

申请号：US15595056

申请日：2017-05-15

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G11C8/10

CPC classification number: G11C8/18 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/10 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/024 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US09196349B2

公开(公告)日：2015-11-24

申请号：US14341601

申请日：2014-07-25

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C8/00 ,  G11C11/4074 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C11/4074 ,  G11C7/1057 ,  G11C7/222 ,  G11C2207/2227

Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.

Abstract translation: 一种设备包括输出电路，DLL（延迟锁定环路）电路，包括接收第一时钟信号的第一延迟线，并且响应于接收到时钟信号而输出提供给输出电路的第二时钟信号，以及ODT 接通ODT激活信号，并且响应于接收到ODT激活信号而输出提供给输出电路的ODT输出信号，以将输出电路设置为电阻终止状态，并且包括第二延迟的ODT电路 线路被配置为由等效延迟量等效于第一延迟线的延迟量由DLL电路设置，ODT输出信号在ODT激活信号处于活动状态的第一时间段期间 通过被设置了等效延迟量的第二延迟线传送而产生。

公开(公告)号：US09053779B2

公开(公告)日：2015-06-09

申请号：US14169442

申请日：2014-01-31

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Ryuji Takishita ,  Takeshi Konno

IPC: H03B19/00 ,  G11C7/22 ,  H03L7/081 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/4096 ,  G11C2207/2227 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818

Abstract: A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.

Abstract translation: 半导体器件包括被配置为接收第一时钟信号的第一输入端子，被配置为分别接收第一控制信号的第一控制端子，输出端子，每个包括耦合到第一输入端子的输入节点的反相器，耦合到 所述第一控制端子中的相应一个和耦合到所述输出端子的输出节点，所述第一反相器中的每一个被配置为被控制以响应于所述第一控制信号中的相应一个而将反相的第一时钟信号输出到所述输出端子 提供给对应的一个控制节点，以及附加的第一反相器，包括耦合到第一输入端的输入节点和耦合到输出端的输出节点，附加的第一反相器没有任何其它控制节点以输出反相 第一个时钟信号输出到输出端。

公开(公告)号：US20210358541A1

公开(公告)日：2021-11-18

申请号：US17362822

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Yasuo Satoh ,  Kenji Mae

IPC: G11C11/406 ,  H03L7/081

Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.