公开(公告)号：US12080350B2

公开(公告)日：2024-09-03

申请号：US17890912

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Riccardo Muzzetto

IPC: G11C11/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26

Abstract: The present disclosure includes apparatuses, methods, and systems for balancing data in memory. An embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a Knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.

公开(公告)号：US12056061B2

公开(公告)日：2024-08-06

申请号：US17663121

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Federica Cresci

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F17/16

CPC classification number: G06F12/1441 ,  G06F12/0238 ,  G06F12/1483 ,  G06F17/16

Abstract: Methods, systems, and devices for address scrambling by linear maps in Galois fields are described. For instance, a device may determine a bijective matrix based on a power up condition. In some examples, the device may determine the bijective matrix based on a seed value and/or may select the matrix from among a set of bijective matrices. In some examples, the bijective matrix may have at least one column and/or one row that has at least two non-zero elements. The device may generate a first address of a first address space based on applying the matrix (e.g., each column of the matrix) to at least a portion of a second address of a second address space and may access a memory array of the device based on generating the first address.

公开(公告)号：US12039176B2

公开(公告)日：2024-07-16

申请号：US17952614

申请日：2022-09-26

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0679

Abstract: The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

公开(公告)号：US20240062824A1

公开(公告)日：2024-02-22

申请号：US17890912

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Riccardo Muzzetto

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26

Abstract: The present disclosure includes apparatuses, methods, and systems for balancing data in memory. An embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a Knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.

公开(公告)号：US20240007265A1

公开(公告)日：2024-01-04

申请号：US18215479

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Niccolò Izzo ,  Marco Sforzin

IPC: H04L9/06 ,  H04L9/32 ,  G06F21/64

CPC classification number: H04L9/0618 ,  H04L9/32 ,  G06F21/64

Abstract: A memory system can be provided with error detection capabilities at various levels and authentication and integrity check capabilities in parallel with data security schemes. The error detection capabilities can check for any errors not only on data paths within a memory controller, but also on data stored in memory devices. The authentication capabilities provided in parallel with the data security schemes can ensure/strengthen data integrity of the memory system to be compliant with standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).

公开(公告)号：US20240005010A1

公开(公告)日：2024-01-04

申请号：US18215462

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: G06F21/60 ,  G06F21/31 ,  G06F11/10

CPC classification number: G06F21/602 ,  G06F21/31 ,  G06F11/1068

Abstract: A memory controller can operate to provide various data protection schemes without a need of a cache. A unit of data transfer between the memory controller and memory devices can correspond to a size of data corresponding to a host read and/or write command. The memory controller operating without a cache can still ensure data integrity of the memory system to be compliant with standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).

公开(公告)号：US20230367721A1

公开(公告)日：2023-11-16

申请号：US17663121

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Federica Cresci

IPC: G06F12/14 ,  G06F12/02 ,  G06F17/16

CPC classification number: G06F12/1441 ,  G06F12/1483 ,  G06F12/0238 ,  G06F17/16

Abstract: Methods, systems, and devices for address scrambling by linear maps in Galois fields are described. For instance, a device may determine a bijective matrix based on a power up condition. In some examples, the device may determine the bijective matrix based on a seed value and/or may select the matrix from among a set of bijective matrices. In some examples, the bijective matrix may have at least one column and/or one row that has at least two non-zero elements. The device may generate a first address of a first address space based on applying the matrix (e.g., each column of the matrix) to at least a portion of a second address of a second address space and may access a memory array of the device based on generating the first address.

公开(公告)号：US11733913B2

公开(公告)日：2023-08-22

申请号：US17677586

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Marco Sforzin ,  Paolo Amato

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0602 ,  G06F3/0673

Abstract: Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

公开(公告)号：US20230207004A1

公开(公告)日：2023-06-29

申请号：US16971053

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0038 ,  G11C13/0097 ,  G11C2013/0054 ,  G11C2213/71

Abstract: Devices, systems and methods for adaptively controlling a reset current of a memory cell are described. A system comprises: a mirror circuit with one branch coupled with a top electrode of the memory cell and the other branch coupled with one end of a resistive reference, and wherein a bottom electrode of the memory cell is coupled to a reference potential, the other end of the resistive reference is provided with a first electric potential; a control circuit; and a feedback circuit for feeding an electric potential to the top electrode of the memory cell.

公开(公告)号：US11687273B2

公开(公告)日：2023-06-27

申请号：US17489336

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Marco Sforzin ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.