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公开(公告)号：US10579307B2
公开(公告)日：2020-03-03
申请号：US16566545
申请日：2019-09-10
发明人： Michael G. Miller , Kishore Kumar Muchherla , Harish Reddy Singidi , Sampath Ratnam , Renato Padilla, Jr. , Gary F. Besinga , Peter Sean Feeley
摘要： Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
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公开(公告)号：US10366763B2
公开(公告)日：2019-07-30
申请号：US15799616
申请日：2017-10-31
发明人： Harish Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
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公开(公告)号：US10283205B2
公开(公告)日：2019-05-07
申请号：US15571232
申请日：2017-09-30
发明人： Ashutosh Malshe , Harish Singidi , Kishore Kumar Muchherla , Michael G. Miller , Sampath Ratnam , John Zhang , Jie Zhou
摘要： Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
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公开(公告)号：US20180374549A1
公开(公告)日：2018-12-27
申请号：US15633377
申请日：2017-06-26
发明人： Renato C. Padilla , Jung Sheng Hoei , Michael G. Miller , Roland J. Awusie , Sampath K. Ratnam , Kishore Kumar Muchherla , Gary F. Besinga , Ashutosh Malshe , Harish R. Singidi
IPC分类号： G11C16/34
CPC分类号： G11C16/3427 , G11C11/5642 , G11C16/3422 , G11C16/3431
摘要： A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
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15.发明申请公开(公告)号：US20180081543A1
公开(公告)日：2018-03-22
申请号：US15269518
申请日：2016-09-19
发明人： Kishore K. Muchherla , Ashutosh Malshe , Sampath K. Ratnam , Peter Feeley , Michael G. Miller , Christopher S. Hale , Renato C. Padilla
IPC分类号： G06F3/06 , G06F12/0893
CPC分类号： G06F3/0604 , G06F3/064 , G06F3/0653 , G06F3/0679 , G06F11/34 , G06F12/0246 , G06F12/0888 , G06F12/0893 , G06F2201/885 , G06F2212/1016 , G06F2212/1044 , G06F2212/222 , G06F2212/502 , G06F2212/601 , G06F2212/7205 , G06F2212/7206
摘要： A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.
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公开(公告)号：US09921898B1
公开(公告)日：2018-03-20
申请号：US15390833
申请日：2016-12-27
发明人： Michael G. Miller , Ashutosh Malshe , Violante Moschiano , Peter Feeley , Gary F. Besinga , Sampath K. Ratnam , Walter Di-Francesco , Renato C. Padilla, Jr. , Yun Li , Kishore Kumar Muchherla
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/0751 , G06F11/0772 , G06F11/079
摘要： Apparatus and methods of operating such apparatus include iteratively programming a group of memory cells to respective desired data states, wherein a particular memory cell is configured to store overhead data and a different memory cell is configured to store user data; determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, changing the desired data state of the particular memory cell before continuing with the programming. Apparatus and methods of operating such apparatus further include reading a data state of a particular memory cell of a last written page of memory cells, and marking the page as affected by power loss during a programming operation if the particular memory cell has any data state other than a particular data state.
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公开(公告)号：US20220351796A1
公开(公告)日：2022-11-03
申请号：US17867538
申请日：2022-07-18
发明人： Renato C. Padilla , Sampath K. Ratnam , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Gary F. Besinga , Michael G. Miller , Tawalin Opastrakoon
摘要： A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.
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公开(公告)号：US11456037B2
公开(公告)日：2022-09-27
申请号：US17318603
申请日：2021-05-12
发明人： Harish Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
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公开(公告)号：US20220276791A1
公开(公告)日：2022-09-01
申请号：US17747548
申请日：2022-05-18
发明人： Michael G. Miller , Gary F. Besinga
IPC分类号： G06F3/06
摘要： An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.
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公开(公告)号：US10942796B2
公开(公告)日：2021-03-09
申请号：US16544190
申请日：2019-08-19
发明人： Michael G. Miller , Ashutosh Malshe , Violante Moschiano , Peter Feeley , Gary F. Besinga , Sampath K. Ratnam , Walter Di-Francesco , Renato C. Padilla, Jr. , Yun Li , Kishore Kumar Muchherla
IPC分类号： G11C11/34 , G06F11/07 , G06F3/06 , G06F11/10 , G11C11/56 , G11C16/10 , G11C16/22 , G11C16/30 , G11C16/34 , G11C5/14
摘要： Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
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