公开(公告)号：US11106372B2

公开(公告)日：2021-08-31

申请号：US15929883

申请日：2020-05-27

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller

IPC: G06F3/06

Abstract: An asynchronous power loss (APL) event is determined to occur. A first erased page (FEP) in a block of a memory device is determined and a last written page (LWP) is determined from the FEP. Data is read from the LWP and peer pages corresponding to the LWP. The data is copied to a temporary area in the memory device and a write pointer is incremented by a deterministic number of pages in the block. Data from the temporary area is copied to a page location in the block identified by the write pointer and the write pointer is incremented by the deterministic number of pages again. A host system is notified that the memory device is ready for a subsequent programming operation after the APL event.

公开(公告)号：US11042306B2

公开(公告)日：2021-06-22

申请号：US16420505

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

公开(公告)号：US20210133099A1

公开(公告)日：2021-05-06

申请号：US17149349

申请日：2021-01-14

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Daniel J. Hubbard ,  Renato C. Padilla ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G06F12/02 ,  G06F3/06

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

公开(公告)号：US10977186B2

公开(公告)日：2021-04-13

申请号：US15819941

申请日：2017-11-21

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Michael G. Miller ,  Xiaoxiao Zhang ,  Jung Sheng Hoei

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/56 ,  G06F11/07

Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.

公开(公告)号：US10579307B2

公开(公告)日：2020-03-03

申请号：US16566545

申请日：2019-09-10

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Sampath Ratnam ,  Renato Padilla, Jr. ,  Gary F. Besinga ,  Peter Sean Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/08

Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.

公开(公告)号：US10366763B2

公开(公告)日：2019-07-30

申请号：US15799616

申请日：2017-10-31

Applicant: Micron Technology, Inc.

Inventor： Harish Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC: G11C16/26 ,  G11C16/08

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US10283205B2

公开(公告)日：2019-05-07

申请号：US15571232

申请日：2017-09-30

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Harish Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  John Zhang ,  Jie Zhou

IPC: G06F12/00 ,  G11C16/26 ,  G06F12/02 ,  G06F11/07 ,  G11C7/06 ,  G11C16/34 ,  G06F11/22

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US20180374549A1

公开(公告)日：2018-12-27

申请号：US15633377

申请日：2017-06-26

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Jung Sheng Hoei ,  Michael G. Miller ,  Roland J. Awusie ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Gary F. Besinga ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5642 ,  G11C16/3422 ,  G11C16/3431

Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

公开(公告)号：US20180081543A1

公开(公告)日：2018-03-22

申请号：US15269518

申请日：2016-09-19

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F12/0893

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.

公开(公告)号：US09921898B1

公开(公告)日：2018-03-20

申请号：US15390833

申请日：2016-12-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, Jr. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G11C16/04 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079

Abstract: Apparatus and methods of operating such apparatus include iteratively programming a group of memory cells to respective desired data states, wherein a particular memory cell is configured to store overhead data and a different memory cell is configured to store user data; determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, changing the desired data state of the particular memory cell before continuing with the programming. Apparatus and methods of operating such apparatus further include reading a data state of a particular memory cell of a last written page of memory cells, and marking the page as affected by power loss during a programming operation if the particular memory cell has any data state other than a particular data state.