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    Apparatuses and methods for concurrently accessing different memory planes of a memory
    11.
    发明授权
    Apparatuses and methods for concurrently accessing different memory planes of a memory 有权

    公开(公告)号：US10755755B2

    公开(公告)日：2020-08-25

    申请号：US16109628

    申请日：2018-08-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G06F12/02 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    MEMORY DEVICES HAVING DIFFERENTLY CONFIGURED BLOCKS OF MEMORY CELLS
    12.
    发明申请
    MEMORY DEVICES HAVING DIFFERENTLY CONFIGURED BLOCKS OF MEMORY CELLS 审中-公开

    公开(公告)号：US20190340066A1

    公开(公告)日：2019-11-07

    申请号：US16516611

    申请日：2019-07-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G06F12/06 ,  G11C16/04 ,  G06F12/02 ,  G11C16/10 ,  G11C11/56

    Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.

    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY
    15.
    发明申请
    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 审中-公开
    用于同时访问存储器的不同存储器的设备和方法

    公开(公告)号：US20160026565A1

    公开(公告)日：2016-01-28

    申请号：US14340976

    申请日：2014-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Tommaso Vali ,  Andrea Giovanni Xotta ,  Umberto Siciliani ,  Luca DeSantis ,  Michele Incarnati

    IPC: G06F12/06 ,  G06F12/02

    CPC classification number: G06F12/0646 ,  G06F12/023 ,  G06F12/0238 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/7208

    Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.

    Abstract translation: 本文公开了同时访问不同存储器平面的装置和方法。 示例性设备可以包括与被配置为维护与多个存储器命令和地址对中的每一个相关联的相应信息的队列相关联的控制器。 控制器被配置为基于由队列维护的信息从多个存储器命令和地址对中选择一组存储器命令和地址对。 该示例设备还包括被配置为接收该组存储器命令和地址对的存储器。 存储器被配置为同时执行与该组存储器命令和地址对相关联的存储器访问操作。

    Non-volatile memory programming
    16.
    发明授权
    Non-volatile memory programming 有权
    非易失性存储器编程

    公开(公告)号：US09202586B2

    公开(公告)日：2015-12-01

    申请号：US14554794

    申请日：2014-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Giovanni Santin ,  Michele Incarnati

    IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

    CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.

    Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括将信号施加到与存储器单元相关联的线，该信号是基于数字信息生成的。 该方法还可以包括当信号被施加到线路时，当数字信息具有第一值时，确定存储器单元的状态是否接近目标状态，并且确定存储器单元的状态是否已经达到目标 当数字信息具有第二值时状态。 描述包括附加存储器件和方法的其它实施例。

    ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING
    17.
    发明申请
    ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING 有权
    用于存储器编程的架构和方法

    公开(公告)号：US20140133224A1

    公开(公告)日：2014-05-15

    申请号：US14162278

    申请日：2014-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati ,  Violante Moschiano

    IPC: G11C16/34

    CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C27/02 ,  G11C2211/5642 ,  G11C2211/5646

    Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.

    Abstract translation: 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

    Apparatuses and methods for concurrently accessing different memory planes of a memory
    18.
    发明授权
    Apparatuses and methods for concurrently accessing different memory planes of a memory 有权

    公开(公告)号：US11462250B2

    公开(公告)日：2022-10-04

    申请号：US16986032

    申请日：2020-08-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G06F3/06 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY
    19.
    发明申请
    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 有权

    公开(公告)号：US20210090623A1

    公开(公告)日：2021-03-25

    申请号：US16986032

    申请日：2020-08-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G11C7/22 ,  G11C16/26 ,  G11C16/32

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

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