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公开(公告)号：US20170317585A1
公开(公告)日：2017-11-02
申请号：US15640959
申请日：2017-07-03
Applicant: Micron Technology, Inc.
Inventor： Xiaojiang Guo , Qiang Tang
IPC: H02M3/07 , G11C5/14 , G11C11/4074
CPC classification number: G11C5/147 , G11C5/145 , G11C11/4074 , G11C16/30
Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first output, a second charge pump circuit configured to provide a second output, a plurality of coupling circuits configured to voltage couple and current couple the first output and the second output to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first output and the second output based on the regulated voltage.
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公开(公告)号：US20160259385A1
公开(公告)日：2016-09-08
申请号：US14639375
申请日：2015-03-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang
CPC classification number: G11C5/14 , G06F13/4072 , G06F13/4086 , H03H11/28 , H03K19/0005 , H03K19/017545 , H03K19/018557
Abstract: Integrated circuit devices and methods of operating integrated circuit devices are useful in impedance adjustment. Integrated circuit devices include a signal driver circuit having an output node, a voltage node, and a first termination device and a second termination device connected in parallel between the voltage node and the output node. The first termination device and the second termination device each have a particular configuration of switchable resistances, and different strengths. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance, connecting the node to a second voltage node through a termination device, adjusting a resistance value of the termination device and comparing a resulting voltage level to a reference voltage. The reference voltage has a voltage level different than half-way between a voltage level of the first voltage node and a voltage level of the second voltage node.
Abstract translation: 集成电路器件和操作集成电路器件的方法在阻抗调节中是有用的。 集成电路装置包括具有输出节点，电压节点以及在电压节点和输出节点之间并联连接的第一终端装置和第二终端装置的信号驱动器电路。 第一终端装置和第二终端装置各自具有可切换电阻的特定构造，并且具有不同的强度。 方法包括通过参考电阻将集成电路装置的节点连接到第一电压节点，通过终端装置将节点连接到第二电压节点，调整终端装置的电阻值，并将得到的电压电平与参考电压进行比较 电压。 参考电压具有与第一电压节点的电压电平和第二电压节点的电压电平之间的中间值不同的电压电平。
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公开(公告)号：US20160258997A1
公开(公告)日：2016-09-08
申请号：US14639293
申请日：2015-03-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Xiaojiang Guo , Chang Wan Ha
IPC: G01R31/28
CPC classification number: H04L25/0278 , G06F13/4086 , G11C5/04 , G11C29/025 , G11C29/028 , G11C29/50008
Abstract: Methods of operating integrated circuit devices are useful in testing impedance adjustment. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance and connecting the node to a second voltage node through a termination device, and comparing a voltage level at the node to a reference voltage for at least one resistance value of the termination device. When no available resistance value of the termination device generates a voltage level at the node that is deemed to match the reference voltage, the voltage level of the reference voltage may be altered, and the voltage level at the node may be compared to the altered reference voltage. When the voltage level at the node is deemed to match the altered reference voltage, the termination device may be deemed as passed. Otherwise, the termination device may be deemed as failed.
Abstract translation: 操作集成电路器件的方法可用于测试阻抗调整。 方法包括通过参考电阻将集成电路装置的节点连接到第一电压节点，并通过终端装置将节点连接到第二电压节点，并将节点处的电压电平与至少一个电阻的参考电压进行比较 终端设备的值。 当终端设备的可用电阻值没有产生在被认为与参考电压相匹配的节点处的电压电平时，可以改变参考电压的电压电平，并且将节点处的电压电平与改变的参考值进行比较 电压。 当节点处的电压电平被认为与改变的参考电压相匹配时，终端设备可以被认为是通过的。 否则，终端设备可能被视为失败。
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公开(公告)号：US11538529B2
公开(公告)日：2022-12-27
申请号：US17176345
申请日：2021-02-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Xiaojiang Guo , Guanglei An , Qiang Tang
Abstract: Methods of operating a memory, and memories having a controller configured to cause the memory to perform such methods, include applying a plurality of first voltage levels to an access line, applying a plurality of second voltage levels to a control gate of a string driver connected to the access line for a first portion of the plurality of first voltage levels with each second voltage level of the plurality of second voltage levels being greater than a respective first voltage level by a first voltage differential, and applying a plurality of third voltage levels to the control gate of the string driver for a second portion of the plurality of first voltage levels with each third voltage level of the plurality of third voltage levels being greater than a respective first voltage level by a second voltage differential less than the first voltage differential.
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15.发明授权公开(公告)号：US11410730B2
公开(公告)日：2022-08-09
申请号：US17096055
申请日：2020-11-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Ramin Ghodsi
Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.
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Patent Agency Ranking
公开(公告)号：US11328777B2
公开(公告)日：2022-05-10
申请号：US16734518
申请日：2020-01-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Theodore T. Pekny
Abstract: Methods of operating apparatus, as well as apparatus configured to perform such methods, include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.
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公开(公告)号：US11079946B2
公开(公告)日：2021-08-03
申请号：US16171442
申请日：2018-10-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luigi Pilolli , Ali Feiz Zarrin Ghalam , Guan Wang , Qiang Tang
Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.
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18.发明授权公开(公告)号：US11024388B2
公开(公告)日：2021-06-01
申请号：US16412661
申请日：2019-05-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Xiaojiang Guo , Guanglei An , Qiang Tang
Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line.
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公开(公告)号：US10833656B2
公开(公告)日：2020-11-10
申请号：US15966889
申请日：2018-04-30
Applicant: Micron Technology, Inc.
Inventor： Qiang Tang
Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to determine when one or more duty cycle calibration (DCC) conditions are met. When the DCC condition(s) are met, the clock distortion calibration circuitry is configured adjust a trim value associated with at least one of first and second duty cycles of first and second voltage signals, respectively. In some embodiments, the clock distortion calibration circuitry is configured to calibrate at least one of the first and the second duty cycles of the first and the second voltage signals using the adjusted trim value to account for duty cycle distortion encountered across various voltages and/or temperatures while the electrical circuit devices and/or systems remain in a powered on state.
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公开(公告)号：US10658041B1
公开(公告)日：2020-05-19
申请号：US16205755
申请日：2018-11-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luigi Pilolli , Agatino Massimo Maccarrone , Hoon Choi , Qiang Tang , Ali Feiz Zarrin Ghalam
Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.
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