公开(公告)号：US20150205530A1

公开(公告)日：2015-07-23

申请号：US14675172

申请日：2015-03-31

Applicant: Micron Technology, Inc.

Inventor： Sean Eilert ,  Mark Leinwander ,  Jared Hulbert

IPC: G06F3/06 ,  G06F12/08 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/06 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F9/50 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0831 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1694 ,  G06F13/38 ,  G06F17/30 ,  G06F2003/0692 ,  G06F2212/622 ,  G11C7/00 ,  G11C7/1072 ,  G11C16/00

Abstract: An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.

Abstract translation: 自主子系统接收从主机控制器下载的数据库。 控制器监视子系统中的总线流量和/或分配的资源，并根据监控结果重新分配资源，以动态提高系统性能。

公开(公告)号：US20150033087A1

公开(公告)日：2015-01-29

申请号：US13949560

申请日：2013-07-24

Applicant: Micron Technology, Inc.

Inventor： Todd Marquart ,  Sampath Ratnam ,  Sean Eilert

IPC: G06F11/07

CPC classification number: G06F11/0727 ,  G06F11/1048 ,  G06F2212/7204 ,  G06F2212/7206 ,  G06F2212/7211

Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.

Abstract translation: 在一个实施例中，响应于被认为失败的存储器单元的块，休息存储器单元块。 对于一些实施例，可以选择休息块以用于响应于通过操作。 在其他实施例中，可以再次休息一个休息块，或者可以响应于该操作失败而从进一步使用中永久退休。

公开(公告)号：US20140351630A1

公开(公告)日：2014-11-27

申请号：US14454040

申请日：2014-08-07

Applicant: Micron Technology Inc.

Inventor： Chris Bueb ,  Sean Eilert

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/765 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1072 ,  G11C29/42 ,  G11C29/52 ,  G11C29/808 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

公开(公告)号：US08806303B2

公开(公告)日：2014-08-12

申请号：US14055405

申请日：2013-10-16

Applicant: Micron Technology Inc.

Inventor： Chris Bueb ,  Sean Eilert

IPC: G11C29/00 ,  H03M13/00

CPC classification number: G11C29/765 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1072 ,  G11C29/42 ,  G11C29/52 ,  G11C29/808 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

Abstract translation: 本文公开的主题涉及确定存储器的一部分至少部分地不起作用，代替至少部分非功能性存储器的部分; 以及响应于确定所述存储器的所述部分至少部分地不起作用和/或替换所述至少部分非功能性存储器的所述部分来调整错误检测和/或校正过程。

公开(公告)号：US10432230B2

公开(公告)日：2019-10-01

申请号：US13959308

申请日：2013-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Bueb ,  Sean Eilert

IPC: H03M13/29 ,  H03M13/09

Abstract: Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device.

公开(公告)号：US20180322085A1

公开(公告)日：2018-11-08

申请号：US16025889

申请日：2018-07-02

Applicant: Micron Technology, Inc.

Inventor： Sean Eilert ,  Mark Leinwander

IPC: G06F13/42 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F13/4247 ,  G06F3/06 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/08 ,  G11C13/0004 ,  H01L45/06 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

公开(公告)号：US10083122B2

公开(公告)日：2018-09-25

申请号：US14822750

申请日：2015-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sean Eilert

IPC: G06F12/16 ,  G06F12/1009 ,  G06F11/30 ,  G06F11/14

CPC classification number: G06F12/1009 ,  G06F11/1456 ,  G06F11/302 ,  G06F11/3037 ,  G06F11/3055 ,  G06F2212/1056 ,  G06F2212/206 ,  G06F2212/261

Abstract: Subject matter disclosed herein relates to techniques to perform transactions using a memory device.

公开(公告)号：US10003675B2

公开(公告)日：2018-06-19

申请号：US14094273

申请日：2013-12-02

Applicant: Micron Technology, Inc.

Inventor： Kenneth M Curewitz ,  Sean Eilert ,  Ameen D. Akel ,  Hongyu Wang

IPC: G06F9/38 ,  H04L29/06 ,  G06F3/06

CPC classification number: H04L69/22 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/3885 ,  G06F2003/0697

Abstract: A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.

公开(公告)号：US20170220516A1

公开(公告)日：2017-08-03

申请号：US15489434

申请日：2017-04-17

Applicant: Micron Technology, Inc.

Inventor： Sean Eilert ,  Mark Leinwander

IPC: G06F13/42 ,  H01L45/00 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F13/4247 ,  G06F3/06 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/08 ,  G11C13/0004 ,  H01L45/06 ,  Y02D10/13

Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

公开(公告)号：US10778815B2

公开(公告)日：2020-09-15

申请号：US15989920

申请日：2018-05-25

Applicant: Micron Technology, Inc.

Inventor： Kenneth M Curewitz ,  Sean Eilert ,  Ameen D. Akel ,  Hongyu Wang

IPC: H04L29/06 ,  G06F9/38 ,  G06F3/06

Abstract: A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.